From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEEEF215F49; Mon, 31 Mar 2025 14:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743431786; cv=none; b=fRAtNAXhbWdqQlzRUEhHw7jvkoAfrSxezZigJ3d7Pa/5EOM5z4nsIT72c8jcaEHr/nuXAu47/LFPSmFWKYZw1Rg1n94j6LzsiLdwaZlNMcoQISjZ60YGNFVm7rWmmhz14dpz2z70RSRDCDnX/0UKqyXBd+Qb+ok7uO+P9+Jcypw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743431786; c=relaxed/simple; bh=QQfSJ6URsGQRTmdqKZqvlDNd1JClNHUaKpoKWm2qpLo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eU4RBKj7uTIa2Ii/tjO9ZqhsSS9SUX4CaNw5laoVRcxPaRdlo/WM3YOqVr8Z3pLBZUJ3GH7HG2lbFOTPTlF2nmGBQPf+UC0pzD2UkfFudHO9BCaaECR38XXfsFjGQRZ02gPN35bCRiFbg/+ySdJ9ze0Nz2uOl5IO5rvDAgpfpis= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b21Qdsok; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b21Qdsok" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB4F6C4CEEB; Mon, 31 Mar 2025 14:36:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743431785; bh=QQfSJ6URsGQRTmdqKZqvlDNd1JClNHUaKpoKWm2qpLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b21Qdsok5uFW960xskwtBFN6K6tfDsM+QJEHx668u2IYsxNGKgkdEdr9PunMJ0tCu Fu+Gs3udW5dWlP2tDXV2HDOMICPI/yu5N+zS3S/S4Kv9hTyCngHVPMrCgIQXVeJmIz nvpxWATw1emXZ06Bw8wiSNe0CYjMTd9rOK5TqhTTVLPrYN7lOI2VnzIAFnqUtvblef R7LkAiwO5ccX0vjmqQTdwoPsxx4aFftJxTpBJiq3JhudPhzFhRzTIyJOK+Pf7HL2d1 UfFW8ZQszGAJDcvJhNa6N1lN48j4rS74HklWwmuw8iSGTE7xLrny+Z7sc0SWQXXFb/ aDIHQuwxCLRog== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Douglas Anderson , Dmitry Baryshkov , Trilok Soni , Catalin Marinas , Sasha Levin , will@kernel.org, mark.rutland@arm.com, oliver.upton@linux.dev, shameerali.kolothum.thodi@huawei.com, maz@kernel.org, scott@os.amperecomputing.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.6 6/9] arm64: cputype: Add QCOM_CPU_PART_KRYO_3XX_GOLD Date: Mon, 31 Mar 2025 10:35:59 -0400 Message-Id: <20250331143605.1686243-6-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250331143605.1686243-1-sashal@kernel.org> References: <20250331143605.1686243-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.85 Content-Transfer-Encoding: 8bit From: Douglas Anderson [ Upstream commit 401c3333bb2396aa52e4121887a6f6a6e2f040bc ] Add a definition for the Qualcomm Kryo 300-series Gold cores. Reviewed-by: Dmitry Baryshkov Signed-off-by: Douglas Anderson Acked-by: Trilok Soni Link: https://lore.kernel.org/r/20241219131107.v3.1.I18e0288742871393228249a768e5d56ea65d93dc@changeid Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 488f8e7513495..c8058f91a5bd3 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -119,6 +119,7 @@ #define QCOM_CPU_PART_KRYO 0x200 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 +#define QCOM_CPU_PART_KRYO_3XX_GOLD 0x802 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 @@ -195,6 +196,7 @@ #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD) #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER) +#define MIDR_QCOM_KRYO_3XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_GOLD) #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) -- 2.39.5