From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBD1422A81C; Mon, 31 Mar 2025 14:37:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743431823; cv=none; b=ljeOcFimXKLaUFy/y7SHqH1qLXzB7Ev2MH2YsmAMAAM3NK+YQ1TN90X4lGi/1432fzEBLtDi9uKzwReFos/fRzJA2pyoNwGqd9cy5MHuf8LoiXs6l2V4Iz9LnUsRXFt4yEjTsdW67J6y9PR0vrILWFFClmlcSBaBar3uYBMIJOM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743431823; c=relaxed/simple; bh=PyXYivHPTRgqifzVqcZTLi4bHziQq4FS8J5aLCVCnDE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cdJNGGR7U8lXhbev3R1n3A4EL3rzfWrO13SwpLvsYbA27g//UjaLc1UoyoK87iKhs4Ez9ZdVmvJtet7yPkveRIoFsh7UapMiCWap1xDgxlilDCDQ3dNKVwVg/cbBOfUFEkhZSQjfql884xDPcr5Or11vdSTm6PFtgGkYmD+18Eg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PZVQVmrg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PZVQVmrg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 291C9C4CEE3; Mon, 31 Mar 2025 14:37:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743431823; bh=PyXYivHPTRgqifzVqcZTLi4bHziQq4FS8J5aLCVCnDE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PZVQVmrgMQKiu33+fcP3XefF8IzZikyivEvfSJNjXtwN7hNafqV3ZQSGG6w4Z39i+ rKklL58BkHdPmDLYEtdiKoYp9PBNOaNZbWiSiFiSZDErFtt0MOpB2+y0BxcWCR58zd 2ZwYSZqjXzjju4/b57hrSog4Go/J6mPazlpqmVASgPbZfBEQI2e/vR3vt0SHfKCu1O o1biuA2odCV9g+YPl16p00q+8bjGExTtLT9thOPmQpxNs/0naPIXGVkyzjyQcfEiJh ALcWann3wo+yrq2Ks5m23PMLoSgp0ZSk4Hliim9eSYHAH4Q8ThTVDTkod2hNs6vegs KaNhIretgrGzg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Douglas Anderson , Dmitry Baryshkov , Trilok Soni , Catalin Marinas , Sasha Levin , will@kernel.org, mark.rutland@arm.com, oliver.upton@linux.dev, shameerali.kolothum.thodi@huawei.com, maz@kernel.org, scott@os.amperecomputing.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.15 4/6] arm64: cputype: Add QCOM_CPU_PART_KRYO_3XX_GOLD Date: Mon, 31 Mar 2025 10:36:49 -0400 Message-Id: <20250331143652.1686503-4-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250331143652.1686503-1-sashal@kernel.org> References: <20250331143652.1686503-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.15.179 Content-Transfer-Encoding: 8bit From: Douglas Anderson [ Upstream commit 401c3333bb2396aa52e4121887a6f6a6e2f040bc ] Add a definition for the Qualcomm Kryo 300-series Gold cores. Reviewed-by: Dmitry Baryshkov Signed-off-by: Douglas Anderson Acked-by: Trilok Soni Link: https://lore.kernel.org/r/20241219131107.v3.1.I18e0288742871393228249a768e5d56ea65d93dc@changeid Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 7dfaad0fa17b7..f3729ef92e570 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -111,6 +111,7 @@ #define QCOM_CPU_PART_KRYO 0x200 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 +#define QCOM_CPU_PART_KRYO_3XX_GOLD 0x802 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 @@ -170,6 +171,7 @@ #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD) #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER) +#define MIDR_QCOM_KRYO_3XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_GOLD) #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) -- 2.39.5