From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1412641CB; Thu, 3 Apr 2025 19:04:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743707085; cv=none; b=TujjDO3nxPvxPqQRh+gPrjnZvcma3VX2YAkT7dzz7LRmNyEIUrWwHI80wF/YtrroORvBhAYklCPp2c+jcBDZxeC0emoTsSOwyDG1ANu9Cu6se4HHiDXCGHNhxZvOFmCfKAy4bSkgMSu4aKiCr+PRLNZdkx6XSgv/KaGVuVlnmsg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743707085; c=relaxed/simple; bh=8ewpeq0OK6g4Il4a93bjITEon6bZwlZPoq3eFcyv+ag=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UOXrr/1P4zgnO2RRRQgjPmqdLQ3jPqrvjjQ5f98Qh8GxgdoWKA4UMA5sHYHdTVLojXvcZs15BPvAHFAKsmxyCOf+oM6GBY/b0eRbXfDJ8pINUZsq4nR3N95BRKkBtXVodr0hsN6dYprxgoHrBahpvJ5QmAFIdJhQmmogzeHQjk0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HI9fll22; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HI9fll22" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CFB98C4CEE3; Thu, 3 Apr 2025 19:04:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743707085; bh=8ewpeq0OK6g4Il4a93bjITEon6bZwlZPoq3eFcyv+ag=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HI9fll22r7HFzvtFs/B9Gs7l9zp52qYuzZxG9ab6m/vdxoBA6UAJPQCLEtL3VaByU mSdbGrSOAqtMOcd0AWV7kB5Xmb+e084ZxHEY6GsJvqaPVlAhbBhAzORK6Et6r4M5wP u0Pnm0Vgf/klfSUMnO5QqqdnHxafqUdfryP9S5jR2GK8fx3PFg5ih57Az1d6oorj6P nn0Nf3lmZ2okMwvvokXK4I/MHdBM+pJKbKV1ZRXudyAF20eIrlPv7mvlE8aEHsuG5c SANZZcX1O/mc/mRPGERlDi2ki0//KD1a8Ar6R3CU8iiYQXHuU4oUmmvaiTM5ckSOje LsSMPnQSDgNfw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ciprian Marian Costea , Marc Kleine-Budde , Sasha Levin , mailhol.vincent@wanadoo.fr, haibo.chen@nxp.com, frank.li@nxp.com, u.kleine-koenig@baylibre.com, dimitri.fedrau@liebherr.com, linux-can@vger.kernel.org Subject: [PATCH AUTOSEL 6.13 16/49] can: flexcan: add NXP S32G2/S32G3 SoC support Date: Thu, 3 Apr 2025 15:03:35 -0400 Message-Id: <20250403190408.2676344-16-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250403190408.2676344-1-sashal@kernel.org> References: <20250403190408.2676344-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.13.9 Content-Transfer-Encoding: 8bit From: Ciprian Marian Costea [ Upstream commit 8503a4b1a24d32e95f3a233062e8f1dc0b2052bd ] Add device type data for S32G2/S32G3 SoC. FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt management is different. On S32G2/S32G3 SoC, there are separate interrupts for state change, bus errors, Mailboxes 0-7 and Mailboxes 8-127 respectively. In order to handle this FlexCAN hardware particularity, first reuse the 'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling support. Secondly, use the newly introduced 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two separate mailbox ranges are controlled by independent hardware interrupt lines. Signed-off-by: Ciprian Marian Costea Link: https://patch.msgid.link/20250113120704.522307-4-ciprianmarian.costea@oss.nxp.com Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/flexcan/flexcan-core.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c index a8a4cc4c064d9..b347a1c93536d 100644 --- a/drivers/net/can/flexcan/flexcan-core.c +++ b/drivers/net/can/flexcan/flexcan-core.c @@ -386,6 +386,16 @@ static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = { FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, }; +static const struct flexcan_devtype_data nxp_s32g2_devtype_data = { + .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | + FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | + FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD | + FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_NR_IRQ_3 | + FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | + FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | + FLEXCAN_QUIRK_SECONDARY_MB_IRQ, +}; + static const struct can_bittiming_const flexcan_bittiming_const = { .name = DRV_NAME, .tseg1_min = 4, @@ -2055,6 +2065,7 @@ static const struct of_device_id flexcan_of_match[] = { { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, }, { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, }, + { .compatible = "nxp,s32g2-flexcan", .data = &nxp_s32g2_devtype_data, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, flexcan_of_match); -- 2.39.5