From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93EAE22D795; Thu, 3 Apr 2025 19:18:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743707936; cv=none; b=Dep4abN4PuvsW8LmfR82GkUEsZ6sWRXCIWFXll/N6RkWwnpEgt+ZzKMxN5qao24QTL+QUk9a8kfzqGb9OTUhlmot04bh+tfHtpV2yHOI9eYcMurkdjsip/B/GRiiCl5sT9lR4S+0A695xL4bYfYnIwFg0lsz+FSSRmVviwVDvm8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743707936; c=relaxed/simple; bh=h3QSDis12+DZtZpk48pGRbePdmUzr9aVvoKyNZ1jgwI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jdSdiYg6FAJojuw2zOsQk+sFvfdyDMrDgvkhhe95NBaVqPlKZ5tcKUwxHQ6NL8GrsOxxBD7Ki1WfUfgcH2GTO8V9LyWG9aPa8jOGwWG5q/wSfdjKeTFarieasCp5n0GTpIMBol6N1kcs6dksUpWgj8OlxaXXUpb6MTCpfVJ4BoA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bhm9Uita; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bhm9Uita" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 234A8C4CEE3; Thu, 3 Apr 2025 19:18:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743707936; bh=h3QSDis12+DZtZpk48pGRbePdmUzr9aVvoKyNZ1jgwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bhm9Uitaa0GS+JH179I0+9K35YOrnvMdOK8pV0qxvEuXP0fd8wsnqB+KknlsWvSTM bzVahkoam0E77/8tUkjU5e1NmjtzQA+7lc5feuSO5XDnGZDnCBrPM0Qku5R8slwZwe KL8ZNIqcYE6tMMBsCktyJk8TutVF9S2E9bUJX/oW6rockJTdyHFkw1IJNJjLfLeJhY RGQSJ1UnUvJfB49eip0+utAH+eGHwmI2u1DFRMRtivR/DAm3ifkdEaLUfU1yhLA1tN yxdG0lW5s1Rt1BA07agsk6BJ4bQsdC0RrDtt2GA1ukVVNJo20sdBBbZ1npYpGKKo1j KVlMquZypCklw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: AngeloGioacchino Del Regno , CK Hu , Chun-Kuang Hu , Sasha Levin , p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.6 16/23] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off Date: Thu, 3 Apr 2025 15:18:09 -0400 Message-Id: <20250403191816.2681439-16-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250403191816.2681439-1-sashal@kernel.org> References: <20250403191816.2681439-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.85 Content-Transfer-Encoding: 8bit From: AngeloGioacchino Del Regno [ Upstream commit 473c33f5ce651365468503c76f33158aaa1c7dd2 ] In preparation for adding support for MT8195's HDMI reserved DPI, add calls to clk_prepare_enable() / clk_disable_unprepare() for the TVD clock: in this particular case, the aforementioned clock is not (and cannot be) parented to neither pixel or engine clocks hence it won't get enabled automatically by the clock framework. Please note that on all of the currently supported MediaTek platforms, the TVD clock is always a parent of either pixel or engine clocks, and this means that the common clock framework is already enabling this clock before the children. On such platforms, this commit will only increase the refcount of the TVD clock without any functional change. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-10-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu Signed-off-by: Sasha Levin --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e4a3bd3989d8a..54fc3f819577e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -471,6 +471,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); + clk_disable_unprepare(dpi->tvd_clk); clk_disable_unprepare(dpi->engine_clk); } @@ -487,6 +488,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) goto err_refcount; } + ret = clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_engine; + } + ret = clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -496,6 +503,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; err_pixel: + clk_disable_unprepare(dpi->tvd_clk); +err_engine: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; -- 2.39.5