From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98661227EA0; Thu, 3 Apr 2025 19:18:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743707906; cv=none; b=VwOQQ8//PLWsqf6P+CEOdB8rOnZ5LQEmPxf4UeGWspeBULqQbntVNYmxutjSk9/G+CRv5J4ysTwpeWomqXwBd4GyUSjxYx/cB/NmghHgXUuO2WAXqWB40qRxwQh3JyflM/A6uP1rAb0kgGF8zyevrw5YeKbZ++XjuUPTQpAu9mo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743707906; c=relaxed/simple; bh=otqcOSfMoH3iQE8svAci/APa4hc6+FBjbvDY3rMfqic=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UBZGWrpiJvhvYGEQql3ZYW69FhkRtu4J8bI7vAKaEe3hKjffjZ94mifrCea3ru+SLSrGqksEHaOtNnEwku67//FzBFPEHUoiVhW1N3p2Xsfy7Ya8o51669JrGbbAZbMVl7s6slkTenjGSQG8Jx+Z+xg3YtnImkYYvwM+g6l3ymo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iXIKoKVT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iXIKoKVT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1E47C4CEE8; Thu, 3 Apr 2025 19:18:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743707906; bh=otqcOSfMoH3iQE8svAci/APa4hc6+FBjbvDY3rMfqic=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iXIKoKVTADhpZGsp9dkgLSlbtvh0538C2vQ7AUjU5Oi8+yUnfDbJM4g6pL3leomj9 /n9MCWtTvLm4TO2do8NNd8vRyV/TVf6NEdW4lVMBuxAzkM5JgZok1WvwClq3rML1i3 SIVsZxY28IGTKiLzg+zueOlv5Xmv0FTudD1biIY2EWPrLVzZo4RGrLUL9Uc80K2fW1 zdDGhKG9RnOswAaxc78Bo4PEOHFokjm9EttJXiJMt88NmsGEDmawFEtImUBYLOU9jk 27Yl8JmBUGIamst1LXdlYsKTJIT1uVcWgjws+nmtx0jrsQQ6TBluFE4vSDH1ZZr0gM 16IM+l8koAfHA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Zhikai Zhai , Nicholas Kazlauskas , Zaeem Mohamed , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, christian.koenig@amd.com, airlied@gmail.com, simona@ffwll.ch, martin.leung@amd.com, chiahsuan.chung@amd.com, bhuvanachandra.pinninti@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.6 02/23] drm/amd/display: Update Cursor request mode to the beginning prefetch always Date: Thu, 3 Apr 2025 15:17:55 -0400 Message-Id: <20250403191816.2681439-2-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250403191816.2681439-1-sashal@kernel.org> References: <20250403191816.2681439-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.85 Content-Transfer-Encoding: 8bit From: Zhikai Zhai [ Upstream commit 4a4077b4b63a8404efd6d37fc2926f03fb25bace ] [Why] The double buffer cursor registers is updated by the cursor vupdate event. There is a gap between vupdate and cursor data fetch if cursor fetch data reletive to cursor position. Cursor corruption will happen if we update the cursor surface in this gap. [How] Modify the cursor request mode to the beginning prefetch always and avoid wraparound calculation issues. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Zhikai Zhai Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 22 ++++++++----------- .../gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c | 2 +- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ff38a85c4fa22..e71b79f5a66cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1930,20 +1930,11 @@ static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx) dc->hwss.get_position(&pipe_ctx, 1, &position); vpos = position.vertical_count; - /* Avoid wraparound calculation issues */ - vupdate_start += stream->timing.v_total; - vupdate_end += stream->timing.v_total; - vpos += stream->timing.v_total; - if (vpos <= vupdate_start) { /* VPOS is in VACTIVE or back porch. */ lines_to_vupdate = vupdate_start - vpos; - } else if (vpos > vupdate_end) { - /* VPOS is in the front porch. */ - return; } else { - /* VPOS is in VUPDATE. */ - lines_to_vupdate = 0; + lines_to_vupdate = stream->timing.v_total - vpos + vupdate_start; } /* Calculate time until VUPDATE in microseconds. */ @@ -1951,13 +1942,18 @@ static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx) stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz; us_to_vupdate = lines_to_vupdate * us_per_line; + /* Stall out until the cursor update completes. */ + if (vupdate_end < vupdate_start) + vupdate_end += stream->timing.v_total; + + /* Position is in the range of vupdate start and end*/ + if (lines_to_vupdate > stream->timing.v_total - vupdate_end + vupdate_start) + us_to_vupdate = 0; + /* 70 us is a conservative estimate of cursor update time*/ if (us_to_vupdate > 70) return; - /* Stall out until the cursor update completes. */ - if (vupdate_end < vupdate_start) - vupdate_end += stream->timing.v_total; us_vupdate = (vupdate_end - vupdate_start + 1) * us_per_line; udelay(us_to_vupdate + us_vupdate); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c index 39a57bcd78667..576acf2ce10dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c @@ -44,7 +44,7 @@ void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable) struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable); - REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable); + REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1); } void hubp31_soft_reset(struct hubp *hubp, bool reset) -- 2.39.5