From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BE2A14A09C; Fri, 4 Apr 2025 00:05:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743725154; cv=none; b=LOtQy24/wtvnZoKzTP3xlEzdTm0SsV3cjRVLan4OQN4UAd+Ag9ocuE8cx1p8WEpoLD5sLlqaulYRvTCSo5EKcNybrQeowQp8JTLBR9lkE3+yGMQRuA6Ij6f8BukVFqXWXx/OLp5bKqPHuLG38tB664JW8fLFs3GTqUSAtEdC4RY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743725154; c=relaxed/simple; bh=SAIAvP07XyuGe/Ilj1nav7Mqv8QbExIi9rs/k91UdzY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XPGQmpHbQuHJxkqYl0h0XqDpmyzb2Qd9uvEQ41HDeEOJiWeG8Gouz5qZyThok1HdycFVe+yesYK8HZ+zwDS+17ASbn3fadwKnYzPGr6f2Mx0vgDTnJt8AIFX5DRQShsfHk5qvY0zw+uDVIJtHBLd34ZBNS5WYy1NQ+87oNu2pzs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aChowIxY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aChowIxY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77E74C4CEE5; Fri, 4 Apr 2025 00:05:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743725152; bh=SAIAvP07XyuGe/Ilj1nav7Mqv8QbExIi9rs/k91UdzY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aChowIxYwp7kd5UANEusL6L4gywEaxM56wa9ZgYnkayuyzf9O8nWTaftM+AO8gi7L WhNuhqx+1YWRMYR66plaP6Wvq8FYzf993s5kA/kE3dSvXFnxtZDRW1jb3F+ZYR5s9X QtnRbL8wpgIHpB760s/TsV7AlcK6adCwJcsLOD5ZZyzvSxb/VOEPHM2WAjGgRkCtEV nkNc4ZNw89Na7AGHIuHGde4wEWssHG0QVzB96KNVW6nN22GxhkugGxDWhW54db9FbH 6ROSsJtoxzmtqtbmYYSTxv5ahbk8w4O75nyVA456mMtGivh4yFoZYps5MERUqItoc1 ORr+d8VoXEQWA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Gregory CLEMENT , Thomas Bogendoerfer , Sasha Levin , jiaxun.yang@flygoat.com, dragan.mladjenovic@syrmia.com, arikalo@gmail.com, paulburton@kernel.org, cfu@wavecomp.com, linux-mips@vger.kernel.org Subject: [PATCH AUTOSEL 6.12 04/20] MIPS: cm: Detect CM quirks from device tree Date: Thu, 3 Apr 2025 20:05:24 -0400 Message-Id: <20250404000541.2688670-4-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250404000541.2688670-1-sashal@kernel.org> References: <20250404000541.2688670-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.12.21 Content-Transfer-Encoding: 8bit From: Gregory CLEMENT [ Upstream commit e27fbe16af5cfc40639de4ced67d1a866a1953e9 ] Some information that should be retrieved at runtime for the Coherence Manager can be either absent or wrong. This patch allows checking if some of this information is available from the device tree and updates the internal variable accordingly. For now, only the compatible string associated with the broken HCI is being retrieved. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/mips-cm.h | 22 ++++++++++++++++++++++ arch/mips/kernel/mips-cm.c | 14 ++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 1e782275850a3..6a1de2ebc7b80 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -59,6 +59,16 @@ extern phys_addr_t mips_cm_l2sync_phys_base(void); */ extern int mips_cm_is64; +/* + * mips_cm_is_l2_hci_broken - determine if HCI is broken + * + * Some CM reports show that Hardware Cache Initialization is + * complete, but in reality it's not the case. They also incorrectly + * indicate that Hardware Cache Initialization is supported. This + * flags allows warning about this broken feature. + */ +extern bool mips_cm_is_l2_hci_broken; + /** * mips_cm_error_report - Report CM cache errors */ @@ -97,6 +107,18 @@ static inline bool mips_cm_present(void) #endif } +/** + * mips_cm_update_property - update property from the device tree + * + * Retrieve the properties from the device tree if a CM node exist and + * update the internal variable based on this. + */ +#ifdef CONFIG_MIPS_CM +extern void mips_cm_update_property(void); +#else +static void mips_cm_update_property(void) {} +#endif + /** * mips_cm_has_l2sync - determine whether an L2-only sync region is present * diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 3eb2cfb893e19..9cfabaa94d010 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -14,6 +15,7 @@ void __iomem *mips_gcr_base; void __iomem *mips_cm_l2sync_base; int mips_cm_is64; +bool mips_cm_is_l2_hci_broken; static char *cm2_tr[8] = { "mem", "gcr", "gic", "mmio", @@ -237,6 +239,18 @@ static void mips_cm_probe_l2sync(void) mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE); } +void mips_cm_update_property(void) +{ + struct device_node *cm_node; + + cm_node = of_find_compatible_node(of_root, NULL, "mobileye,eyeq6-cm"); + if (!cm_node) + return; + pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken"); + mips_cm_is_l2_hci_broken = true; + of_node_put(cm_node); +} + int mips_cm_probe(void) { phys_addr_t addr; -- 2.39.5