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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2025 17:36:23.1358 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a504787-a3fe-462e-8f1e-08dd75fab732 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6553 IOMMU Capability registers defines capabilities of IOMMU and information needed for initialising MMIO registers and device table. This is useful to dump these registers for debugging IOMMU related issues. e.g. -> To get capability registers value at offset 0x10 for iommu (say, iommu00) # echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability # cat /sys/kernel/debug/iommu/amd/iommu00/capability Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/debugfs.c | 51 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 7cbc25eaa74a..1666a460d030 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -795,6 +795,7 @@ struct amd_iommu { /* DebugFS Info */ struct dentry *debugfs; int mmio_offset; + int cap_offset; #endif /* IOPF support */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 520377ab6731..5ac12c3fe069 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -58,6 +58,54 @@ static int iommu_mmio_show(struct seq_file *m, void *unused) } DEFINE_SHOW_STORE_ATTRIBUTE(iommu_mmio); +static ssize_t iommu_capability_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct seq_file *m = filp->private_data; + struct amd_iommu *iommu = m->private; + int ret; + + iommu->cap_offset = -1; + + if (cnt > OFS_IN_SZ) + return -EINVAL; + + ret = kstrtou32_from_user(ubuf, cnt, 0, &iommu->cap_offset); + if (ret) + return ret; + + /* Capability register at offset 0x14 is the last IOMMU capability register. */ + if (iommu->cap_offset > 0x14) { + iommu->cap_offset = -1; + return -EINVAL; + } + + return cnt; +} + +static int iommu_capability_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu = m->private; + u32 value; + int err; + + if (iommu->cap_offset < 0) { + seq_puts(m, "Please provide capability register's offset in the range [0x00 - 0x14]\n"); + return 0; + } + + err = pci_read_config_dword(iommu->dev, iommu->cap_ptr + iommu->cap_offset, &value); + if (err) { + seq_printf(m, "Not able to read capability register at 0x%x\n", iommu->cap_offset); + return 0; + } + + seq_printf(m, "Offset:0x%x Value:0x%08x\n", iommu->cap_offset, value); + + return 0; +} +DEFINE_SHOW_STORE_ATTRIBUTE(iommu_capability); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -67,11 +115,14 @@ void amd_iommu_debugfs_setup(void) for_each_iommu(iommu) { iommu->mmio_offset = -1; + iommu->cap_offset = -1; snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); iommu->debugfs = debugfs_create_dir(name, amd_iommu_debugfs); debugfs_create_file("mmio", 0644, iommu->debugfs, iommu, &iommu_mmio_fops); + debugfs_create_file("capability", 0644, iommu->debugfs, iommu, + &iommu_capability_fops); } } -- 2.25.1