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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , , CC: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Waiman Long , Swapnil Sapkal , "Dhananjay Ugwekar" , Huang Rui , "Perry Yuan" , K Prateek Nayak Subject: [PATCH v2 0/4] sched/fair: Dynamic asym priority support Date: Wed, 9 Apr 2025 05:34:42 +0000 Message-ID: <20250409053446.23367-1-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F2:EE_|DS4PR12MB9587:EE_ X-MS-Office365-Filtering-Correlation-Id: e3abeff2-fb00-4bdb-ff17-08dd77284ad7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024|921020|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mZEc5195P6FPV9wwboktyx0udzLQxeVGZF1O2r0OvJKTw9U2RZrCYzP3ZWC2?= =?us-ascii?Q?vPfaEmoJPaQmueyBZXw5t5keVtfZOP3CrC3trWxffGAGgb4VTEfokD3Yldsr?= =?us-ascii?Q?jGJF4M5M9SVl4r58kZjzPxRRnh4Rj1mSYvj7HWepVhHONtxmnAdW/IhJvsgo?= =?us-ascii?Q?v4H6P1HTD28xhXPW4VuQi3O3HoYTwV6iiAaUSBeXPc4dJABV8WGLSv/6/ATs?= =?us-ascii?Q?yn38NwegleAzVoKc+1DxFO6Q4yH3G5k3W+/g1OANfBSA7jraEDOWz67RaTXC?= =?us-ascii?Q?/0pJnqc2krQWOAUDHMixoF3CaR6a9R7itPtAdC8WMTGZrjRZIQ574FKwuVHB?= =?us-ascii?Q?v92f2QHIqhJPlJ0hqY0meLjAc+Qz4BeWGqsDnHfPQHkijFUq6ymVUU0RZg1q?= =?us-ascii?Q?czr34tL/omf+vEgQUajRs0tw0+VeGDZeCmy9nMYwqABeihSrDYhF7pYEk1vL?= =?us-ascii?Q?OY/L49v5/cBSipy/+MxvsMyBjcp/mpa3SDCQ4RvQZMTAL20uhtf9SAuj8Gxt?= =?us-ascii?Q?pRpdZOP+3/yGYeqp43It0mNLg6hCoeGE+BTYc7CjoRbdR9iaqqVFluVKkGlu?= =?us-ascii?Q?TRIsa6V4y8uWXBApBbCSXmrFHbC+SIrbzuecyhXz28pjugnRcgzUxreInDC3?= =?us-ascii?Q?M5LPXhxqD3tDNGr1pDJ9LW7cSil/kIL+mpOW63CF/VKxrSkjk+t4yZttl01s?= =?us-ascii?Q?ZJIvjw8dkTSUGppf2/riTlv0WoiqNSDdOW13ac9c1w2Co1XshOPAcz0runtx?= =?us-ascii?Q?mPBnPYPHsbd9ZLi8wI5r6v/TO/yjFs2HQMgFraAlaNsx4uR0OK3Ch4u2eTH6?= =?us-ascii?Q?9qfQUj97DYO3yRK7tjnIs4R+/PhxKr0Eyz0uojNeyBQV5SNMS4KZY3KbxZIH?= =?us-ascii?Q?0YtmCp2UEw8dH43Tg1Q23+NrVJY7vcdN48X+tP61ShLOwqU6MZne5pmr90k1?= =?us-ascii?Q?nwPQxaZp9kUxjqeJrk8lhPNr2VBZMUv5fNz1jStnw0tEJ0isUwN0FLuirkL4?= =?us-ascii?Q?uOTcOo9ZESNBVcb7OTP2VTFH93g3JH+Ylzp0OyPKcsIHcV6GlHPf9nieio0o?= =?us-ascii?Q?IbR4pR7VGVJIqAOUT1fnr7s28wd18C6UD0vYqYpwkyGy1zCGQ6T3Dfjtria5?= =?us-ascii?Q?c3u2b5rB4wpJGx1nKIhnt2D1lPzZw8uKZncu6h6JEOWKICN0JZLkmbfw4vwd?= =?us-ascii?Q?hYYfLfmP6FfnwayCa4fx1Sevl61BxPrpZlGDRYTVTySehFPLZEGWT1Op+SqF?= =?us-ascii?Q?yO+73PoxzOGebSZh9skPXUZ/sI4LW+gPMciFneo09h13iP6FKgVBCf/P+dbf?= =?us-ascii?Q?5Bylt7/k990pKfd0uG1XO1O3D3EzpQgG3L7VIjys8ADZFyKK2S4Br8Q7kg4q?= =?us-ascii?Q?334gpsadgBBbla4UQwGFMWtpPUxGYUA5eaKvjiX9L2CLH/BzblQuIOhWK5TE?= =?us-ascii?Q?ZTZ+Yj3XwRJtuUSSw8xLX1Um/pLaajPaP/U/mlk15BiCn9HfqVJmmJmpp64o?= =?us-ascii?Q?xM8FRDSqNLf0ATI=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024)(921020)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 05:35:09.3139 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3abeff2-fb00-4bdb-ff17-08dd77284ad7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9587 A subset of AMD Processors which support Preferred Core rankings can have these rankings change at runtime to bias the load balancing towards CPUs with higher frequency / larger cache. In the current implementation, the CPU with the highest asym priority - "asym_prefer_cpu" is cached in the sched_group struct when building the sched domain hierarchy. Previous approach in [1] to uncache the "asym_prefer_cpu" and compute it during load balancing was not popular as it not only lost the benefits of caching but also added more overhead in update_sg_lb_stats(). At OSPM'25, Vincent suggested retaining "asym_prefer_cpu" but updating it dynamically when the asym priority changes without needing to rebuild the entire sched domain hierarchy. Introduce sched_update_asym_prefer_cpu() which traverses the local hierarchy on priority change and recomputes the "asym_prefer_cpu". Since sched_group for !SD_OVERLAP domains are shared by all the CPUs in sched_group_span(sg) (see get_group() in kernel/sched/topology.c), updating the "asym_prefer_cpu" in the groups of the local hierarchy ensures all the CPUs in the group see the updated value. Groups of SD_OVERLAP domains can be supported too but this involves moving "asym_prefer_cpu" to "sg->sgc" which adds another level of indirection. Since there isn't a use case currently where both SD_OVERLAP and SD_ASYM_PACKING is set for the same sched domain, v2 keeps things simple only extends dynamic updates to groups of !SD_OVERLAP domains. If this future looking enablement is required, please do let me know. Printing the "asym_prefer_cpu" for the local group in debugfs has not only proved useful to debug this series but has also helped uncover other unrelated issues like [2] which is why I've retained it for inclusion. This series is based on: git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git sched/core at commit 6432e163ba1b ("sched/isolation: Make use of more than one housekeeping cpu") [1] https://lore.kernel.org/lkml/20241211185552.4553-9-kprateek.nayak@amd.com/ [2] https://lore.kernel.org/lkml/20250409030004.23008-1-kprateek.nayak@amd.com/ --- Changelog: v1..v2: o New approach that introduces sched_update_asym_prefer_cpu() to update the "asym_prefer_cpu" dynamically on ranking change without rebuilding the sched domain hierarchy. --- K Prateek Nayak (4): sched/fair: Use READ_ONCE() to read sg->asym_prefer_cpu sched/topology: Introduce sched_update_asym_prefer_cpu() cpufreq/amd-pstate: Update asym_prefer_cpu when core rankings change sched/debug: Print the local group's asym_prefer_cpu drivers/cpufreq/amd-pstate.c | 4 ++- include/linux/sched/topology.h | 6 ++++ kernel/sched/debug.c | 4 +++ kernel/sched/fair.c | 5 +-- kernel/sched/topology.c | 58 ++++++++++++++++++++++++++++++++++ 5 files changed, 74 insertions(+), 3 deletions(-) base-commit: 6432e163ba1b7d80b5876792ce53e511f041ab91 -- 2.34.1