From: Liu Runrun <liurunrun@uniontech.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, liurunrun@uniontech.com,
mingo@kernel.org, ryan.roberts@arm.com, catalin.marinas@arm.com,
akpm@linux-foundation.org, kirill.shutemov@linux.intel.com,
arnd@arndb.de
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arch@vger.kernel.org, wangyuli@uniontech.com,
zhanjun@uniontech.com, niecheng1@uniontech.com
Subject: [PATCH] RISC-V: Fix PCI I/O port addressing for MMU-less configurations
Date: Fri, 11 Apr 2025 10:34:08 +0800 [thread overview]
Message-ID: <20250411023408.185150-1-liurunrun@uniontech.com> (raw)
This patch addresses the PCI I/O port address handling in RISC-V's
port-mapped I/O emulation routines when the MMU is not enabled.
The changes ensure that:
1. For non-MMU systems, the PCI I/O port addresses are properly
calculated in marcos inX and outX when PCI_IOBASE is not
defined, this avoids the null pointer calculating warning
from the compiler.
2. In asm-generic/io.h, function ioport_map(), casting PCI_IOPORT
to type "long" firstly makes it could compute with variable addr
directly, which avoids the null pointer calculating warning when
PCI_IOPORT is a null pointer in some case.
The original implementation used `PCI_IOBASE + (addr)` for MMU-enabled
systems, but failed to handle non-MMU cases correctly. This change adds
conditional compilation guards (#ifdef CONFIG_MMU) to differentiate
between MMU and non-MMU environments, providing consistent behavior
for both scenarios.
Fixes: 9cc205e3c17d ("RISC-V: Make port I/O string accessors actually work")
Reported-by: WangYuli <wangyuli@uniontech.com>
Signed-off-by: Liu Runrun <liurunrun@uniontech.com>
---
arch/riscv/include/asm/io.h | 22 +++++++++++++++++++++-
include/asm-generic/io.h | 3 ++-
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index a0e51840b9db..d5181bb02c98 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -101,9 +101,15 @@ __io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
__io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
+#ifdef CONFIG_MMU
#define insb(addr, buffer, count) __insb(PCI_IOBASE + (addr), buffer, count)
#define insw(addr, buffer, count) __insw(PCI_IOBASE + (addr), buffer, count)
#define insl(addr, buffer, count) __insl(PCI_IOBASE + (addr), buffer, count)
+#else
+#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
+#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
+#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
+#endif /* CONFIG_MMU */
__io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
__io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
@@ -115,23 +121,37 @@ __io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
__io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
__io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
__io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
+#ifdef CONFIG_MMU
#define outsb(addr, buffer, count) __outsb(PCI_IOBASE + (addr), buffer, count)
#define outsw(addr, buffer, count) __outsw(PCI_IOBASE + (addr), buffer, count)
#define outsl(addr, buffer, count) __outsl(PCI_IOBASE + (addr), buffer, count)
+#else
+#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
+#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
+#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
+#endif /* CONFIG_MMU */
#ifdef CONFIG_64BIT
__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
#define readsq(addr, buffer, count) __readsq(addr, buffer, count)
__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
+#ifdef CONFIG_MMU
#define insq(addr, buffer, count) __insq(PCI_IOBASE + (addr), buffer, count)
+#else
+#define insq(addr, buffer, count) __insq((void __iomem *)(long)addr, buffer, count)
+#endif /* CONFIG_MMU */
__io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
#define writesq(addr, buffer, count) __writesq(addr, buffer, count)
__io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
+#ifdef CONFIG_MMU
#define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
-#endif
+#else
+#define outsq(addr, buffer, count) __outsq((void __iomem *)(long)addr, buffer, count)
+#endif /* CONFIG_MMU */
+#endif /* CONFIG_64BIT */
#include <asm-generic/io.h>
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 11abad6c87e1..c0409188bb5e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -1172,7 +1172,8 @@ static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
port &= IO_SPACE_LIMIT;
- return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
+ return (port > MMIO_UPPER_LIMIT) ?
+ NULL : (void __iomem *)((unsigned long)PCI_IOBASE + port);
}
#define ARCH_HAS_GENERIC_IOPORT_MAP
#endif
--
2.49.0
next reply other threads:[~2025-04-11 2:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-11 2:34 Liu Runrun [this message]
2025-04-11 5:41 ` Arnd Bergmann
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