From: Akhil P Oommen <quic_akhilpo@quicinc.com>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
"Konrad Dybcio" <konradybcio@kernel.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Viresh Kumar <vireshk@kernel.org>, Nishanth Menon <nm@ti.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Bjorn Andersson <andersson@kernel.org>,
"Maya Matuszczyk" <maccraft123mc@gmail.com>,
Anthony Ruhier <aruhier@mailbox.org>,
Dmitry Baryshkov <lumag@kernel.org>
Cc: <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
<linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v5 2/7] drm/msm/a6xx: Increase HFI response timeout
Date: Sat, 19 Apr 2025 20:21:31 +0530 [thread overview]
Message-ID: <20250419-gpu-acd-v5-2-8dbab23569e0@quicinc.com> (raw)
In-Reply-To: <20250419-gpu-acd-v5-0-8dbab23569e0@quicinc.com>
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Tested-by: Anthony Ruhier <aruhier@mailbox.org>
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index b256092596fbab86d4eb8c17ac7c89cf94827105..d0ddae1617c3213a1bb2cb5c18b8653c5c1689e6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -109,7 +109,7 @@ static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum,
/* Wait for a response */
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
- val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000);
+ val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 1000000);
if (ret) {
DRM_DEV_ERROR(gmu->dev,
--
2.48.1
next prev parent reply other threads:[~2025-04-19 14:52 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-19 14:51 [PATCH v5 0/7] Support for GPU ACD feature on Adreno X1-85 Akhil P Oommen
2025-04-19 14:51 ` [PATCH v5 1/7] drm/msm/adreno: Add support for ACD Akhil P Oommen
2025-04-23 12:21 ` Konrad Dybcio
2025-04-19 14:51 ` Akhil P Oommen [this message]
2025-04-19 14:51 ` [PATCH v5 3/7] drm/msm: a6x: Rework qmp_get() error handling Akhil P Oommen
2025-04-23 13:28 ` Dmitry Baryshkov
2025-05-03 6:59 ` Akhil P Oommen
2025-04-19 14:51 ` [PATCH v5 4/7] drm/msm/adreno: Add module param to disable ACD Akhil P Oommen
2025-04-23 12:25 ` Konrad Dybcio
2025-04-19 14:51 ` [PATCH v5 5/7] dt-bindings: opp: Add v2-qcom-adreno vendor bindings Akhil P Oommen
2025-04-22 8:43 ` Krzysztof Kozlowski
2025-04-19 14:51 ` [PATCH v5 6/7] arm64: dts: qcom: x1e80100: Add ACD levels for GPU Akhil P Oommen
2025-04-19 14:51 ` [PATCH v5 7/7] arm64: dts: qcom: x1e80100: Add OPPs up to Turbo L3 " Akhil P Oommen
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