From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F233238C3D for ; Fri, 25 Apr 2025 09:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745571640; cv=none; b=rQdbkpondRCGLWvK35xK4yK+QY8nH/SiDBl9HYwpP7cofak6hXG+Ls7guPPmeU6It1ZMEdLwyblLJ2CeR5TtNXY4GfjGa7nZc+0h4FRx1F6fSA07nmF99OkBZTZoAhtH4eO0t6erBqxXzfQB8tNU63f9IfsRthxYiNK3vNT5r2U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745571640; c=relaxed/simple; bh=yMv4SY0fnld2VBgAtUr1s5+LhOrGDoyQMSowsDCxdSc=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=n4DRVBfWSuwOYmhPjYxxu7JyAJoUdZ/7RxfqM/7C35bpPga/hUDcX0W6g5H+MOwx5z0oAKmsz4tQZAQFBwTZFpMhZ7k8vJ7FtJmjDAMvHWtU48A5XhTNROzkK2SO/+DBrSM2BdprZL6lEFXr6Lc/cT77ILdB3JE0GHMLJTofauo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4ZkRYF13p0z2Cdb1; Fri, 25 Apr 2025 16:57:05 +0800 (CST) Received: from kwepemd200014.china.huawei.com (unknown [7.221.188.8]) by mail.maildlp.com (Postfix) with ESMTPS id 6328A1400DC; Fri, 25 Apr 2025 17:00:35 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by kwepemd200014.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 25 Apr 2025 17:00:34 +0800 From: Yicong Yang To: , , , CC: , , , , , Subject: [RESEND PATCH v3 0/8] General updates and two new drivers for HiSilicon Uncore PMU Date: Fri, 25 Apr 2025 17:00:21 +0800 Message-ID: <20250425090029.50786-1-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemd200014.china.huawei.com (7.221.188.8) From: Yicong Yang Support new version of DDRC/SLLC PMU identified with updated ACPI HID and register definition. In order to support this, we do a preliminary refactor to initialize device of each version by using driver data of each HID rather than checking the version. This will also make the driver easier to maintain and extend, since only the HID specific information along with the new HID will be added to support the new version without touching the common logic. Two new Uncore PMU drivers is also added to support the monitoring the events of the system bus (by NoC PMU) and the DVM operations (by MN PMU). Change since v2: - Rebase on 6.15-rc1, add Jonathan's tag. Link: https://lore.kernel.org/linux-arm-kernel/20250321073846.23507-1-yangyicong@huawei.com/ Change since v1: - Fold patch which extending the struct hisi_pmu_dev_info into its user - Use bit shift rather than bit mask for SLLC PMU registers configuration - Address other comments by Jonathan, thanks Link: https://lore.kernel.org/linux-arm-kernel/20250218092000.41641-1-yangyicong@huawei.com/ Junhao He (6): drivers/perf: hisi: Simplify the probe process for each DDRC version drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver drivers/perf: hisi: Relax the event number check of v2 PMUs drivers/perf: hisi: Add support for HiSilicon MN PMU driver Yicong Yang (2): drivers/perf: hisi: Support PMUs with no interrupt drivers/perf: hisi: Add support for HiSilicon NoC PMU Documentation/admin-guide/perf/hisi-pmu.rst | 11 + drivers/perf/hisilicon/Makefile | 3 +- drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 354 ++++++++-------- drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 6 +- drivers/perf/hisilicon/hisi_uncore_mn_pmu.c | 355 ++++++++++++++++ drivers/perf/hisilicon/hisi_uncore_noc_pmu.c | 392 ++++++++++++++++++ drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 2 +- drivers/perf/hisilicon/hisi_uncore_pmu.c | 11 +- drivers/perf/hisilicon/hisi_uncore_pmu.h | 2 + drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 220 +++++++--- 10 files changed, 1098 insertions(+), 258 deletions(-) create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn_pmu.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_noc_pmu.c -- 2.24.0