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([2.196.40.180]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a52f8915sm87682015e9.7.2025.04.27.00.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Apr 2025 00:44:12 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Alexandre Torgue , linux-amarula@amarulasolutions.com, Dario Binacchi , Maxime Coquelin , Russell King , linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/8] ARM: stm32: add a new SoC - STM32H747 Date: Sun, 27 Apr 2025 09:43:22 +0200 Message-ID: <20250427074404.3278732-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250427074404.3278732-1-dario.binacchi@amarulasolutions.com> References: <20250427074404.3278732-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The STM32H747 is a dual-core MCU (Cortex-M7 running up to 480 MHz + Cortex-M4 running up to 240 MHz) containing from 1 to 2 Mbytes of Flash memory and 1 Mbyte of internal RAM. Signed-off-by: Dario Binacchi --- arch/arm/mach-stm32/board-dt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index 5dcc4ddd1a56..e6233c8725ae 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -17,6 +17,7 @@ static const char *const stm32_compat[] __initconst = { "st,stm32f746", "st,stm32f769", "st,stm32h743", + "st,stm32h747", "st,stm32h750", "st,stm32mp131", "st,stm32mp133", -- 2.43.0