From: Yabin Cui <yabinc@google.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>, Leo Yan <leo.yan@arm.com>,
Jie Gan <quic_jiegan@quicinc.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Yabin Cui <yabinc@google.com>
Subject: [PATCH v2] coresight: trbe: Save/restore state across CPU low power state
Date: Tue, 29 Apr 2025 16:05:15 -0700 [thread overview]
Message-ID: <20250429230515.1906253-1-yabinc@google.com> (raw)
Similar to ETE, TRBE may lose its context when a CPU enters low
power state. To make things worse, if ETE is restored without
TRBE being restored, we have an enabled source device with no
enabled sink devices, which can cause CPU hang on some devices
(Pixel 9).
This patch adds sink operations to save and restore state for TRBE,
and calls them when saving and restoring state for ETE. This is
to ensure that we always restore the state of TRBE before ETE.
Signed-off-by: Yabin Cui <yabinc@google.com>
---
.../coresight/coresight-etm4x-core.c | 13 ++++-
drivers/hwtracing/coresight/coresight-trbe.c | 58 +++++++++++++++++++
include/linux/coresight.h | 6 ++
3 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 2b8f10463840..aaabbda97afc 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1863,6 +1863,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
{
int ret = 0;
+ struct coresight_device *sink;
/* Save the TRFCR irrespective of whether the ETM is ON */
if (drvdata->trfcr)
@@ -1871,8 +1872,14 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
* Save and restore the ETM Trace registers only if
* the ETM is active.
*/
- if (coresight_get_mode(drvdata->csdev) && drvdata->save_state)
+ if (coresight_get_mode(drvdata->csdev) && drvdata->save_state) {
ret = __etm4_cpu_save(drvdata);
+ if (ret == 0) {
+ sink = coresight_get_percpu_sink(drvdata->cpu);
+ if (sink && sink_ops(sink)->percpu_save)
+ sink_ops(sink)->percpu_save(sink);
+ }
+ }
return ret;
}
@@ -1977,6 +1984,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
{
+ struct coresight_device *sink = coresight_get_percpu_sink(drvdata->cpu);
+
+ if (sink && sink_ops(sink)->percpu_restore)
+ sink_ops(sink)->percpu_restore(sink);
if (drvdata->trfcr)
write_trfcr(drvdata->save_trfcr);
if (drvdata->state_needs_restore)
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index fff67aac8418..d94d1a7a2330 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -115,6 +115,20 @@ static int trbe_errata_cpucaps[] = {
*/
#define TRBE_WORKAROUND_OVERWRITE_FILL_MODE_SKIP_BYTES 256
+/*
+ * struct trbe_save_state: Register values representing TRBE state
+ * @trblimitr - Trace Buffer Limit Address Register value
+ * @trbbaser - Trace Buffer Base Register value
+ * @trbptr - Trace Buffer Write Pointer Register value
+ * @trbsr - Trace Buffer Status Register value
+ */
+struct trbe_save_state {
+ u64 trblimitr;
+ u64 trbbaser;
+ u64 trbptr;
+ u64 trbsr;
+};
+
/*
* struct trbe_cpudata: TRBE instance specific data
* @trbe_flag - TRBE dirty/access flag support
@@ -123,6 +137,8 @@ static int trbe_errata_cpucaps[] = {
* @cpu - CPU this TRBE belongs to.
* @mode - Mode of current operation. (perf/disabled)
* @drvdata - TRBE specific drvdata
+ * @state_needs_restore - Whether TRBE state has been saved and can be restored
+ * @save_state - Saved TRBE state
* @errata - Bit map for the errata on this TRBE.
*/
struct trbe_cpudata {
@@ -133,6 +149,8 @@ struct trbe_cpudata {
enum cs_mode mode;
struct trbe_buf *buf;
struct trbe_drvdata *drvdata;
+ bool state_needs_restore;
+ struct trbe_save_state save_state;
DECLARE_BITMAP(errata, TRBE_ERRATA_MAX);
};
@@ -1187,12 +1205,51 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
return IRQ_HANDLED;
}
+static void arm_trbe_cpu_save(struct coresight_device *csdev)
+{
+ struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
+ struct trbe_save_state *state;
+
+ if (cpudata->mode == CS_MODE_DISABLED)
+ return;
+
+ state = &cpudata->save_state;
+ state->trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
+ state->trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
+ state->trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
+ state->trbsr = read_sysreg_s(SYS_TRBSR_EL1);
+ cpudata->state_needs_restore = true;
+}
+
+static void arm_trbe_cpu_restore(struct coresight_device *csdev)
+{
+ struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
+ struct trbe_save_state *state;
+
+ if (cpudata->state_needs_restore) {
+ /*
+ * To avoid disruption of normal tracing, restore trace
+ * registers only when TRBE lost power (TRBLIMITR == 0).
+ */
+ if (read_sysreg_s(SYS_TRBLIMITR_EL1) == 0) {
+ state = &cpudata->save_state;
+ write_sysreg_s(state->trbbaser, SYS_TRBBASER_EL1);
+ write_sysreg_s(state->trbptr, SYS_TRBPTR_EL1);
+ write_sysreg_s(state->trbsr, SYS_TRBSR_EL1);
+ set_trbe_enabled(cpudata, state->trblimitr);
+ }
+ cpudata->state_needs_restore = false;
+ }
+}
+
static const struct coresight_ops_sink arm_trbe_sink_ops = {
.enable = arm_trbe_enable,
.disable = arm_trbe_disable,
.alloc_buffer = arm_trbe_alloc_buffer,
.free_buffer = arm_trbe_free_buffer,
.update_buffer = arm_trbe_update_buffer,
+ .percpu_save = arm_trbe_cpu_save,
+ .percpu_restore = arm_trbe_cpu_restore,
};
static const struct coresight_ops arm_trbe_cs_ops = {
@@ -1358,6 +1415,7 @@ static void arm_trbe_probe_cpu(void *info)
cpudata->trbe_flag = get_trbe_flag_update(trbidr);
cpudata->cpu = cpu;
cpudata->drvdata = drvdata;
+ cpudata->state_needs_restore = false;
return;
cpu_clear:
cpumask_clear_cpu(cpu, &drvdata->supported_cpus);
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index cfcf6e4707ed..098c04c4a59d 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -362,6 +362,10 @@ enum cs_mode {
* @alloc_buffer: initialises perf's ring buffer for trace collection.
* @free_buffer: release memory allocated in @get_config.
* @update_buffer: update buffer pointers after a trace session.
+ * @percpu_save: saves state when CPU enters idle state.
+ * Only set for percpu sink.
+ * @percpu_restore: restores state when CPU exits idle state.
+ * only set for percpu sink.
*/
struct coresight_ops_sink {
int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
@@ -374,6 +378,8 @@ struct coresight_ops_sink {
unsigned long (*update_buffer)(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config);
+ void (*percpu_save)(struct coresight_device *csdev);
+ void (*percpu_restore)(struct coresight_device *csdev);
};
/**
--
2.49.0.967.g6a0df3ecc3-goog
reply other threads:[~2025-04-29 23:05 UTC|newest]
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