From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A82E29C862; Tue, 29 Apr 2025 23:52:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745970741; cv=none; b=DAbnAo8soJS/4kojY62CqOF7fnyTM3xfMOSklSMJ/XR7Y+4UG9+/sSshUd4L1WUgJY6wLDNevoWqymvEJl+XdCzwwn/57sRG4hxndHtxDPc9n4oA/p0rQ4f1Oe08JLmscaj09/cvOdVxLJ+mGBMSdZ5cDPS6zPm8xiMHC6JCMNg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745970741; c=relaxed/simple; bh=7Mqkh/DfpJaKhMCrCkYPgeCnFVkfSR9IgPhX19vd/Ro=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Jf6DMD9Kl/rfcSZGnLzeimzMJVs7moEjXXXgojK5v6tJybmOD19G6lSME8EFLnrthuirXik9JmxeqBtx9vr0CUN3I8JF6MWeKTDqq6uFnT+SRAa7Npb+MfxdpMOYQwBBYl+SKNJkN69sQ+Wce3XYey7Ao8t1+4mfV4WkbVXg7Q0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h6sP6cDH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h6sP6cDH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F2A0C4CEE3; Tue, 29 Apr 2025 23:52:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745970741; bh=7Mqkh/DfpJaKhMCrCkYPgeCnFVkfSR9IgPhX19vd/Ro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h6sP6cDHtIDcI9pWHM9wlBC1nkzjVniG9pIN7tK2Fhp6dk+MeSjIHu8S5KB0TzAGh Sg6E9OGbl1cCMB5ZuBzZsys51jYJELYIlASV3qHEFz55SgQMKK96eWrr1QHs1NRM4F 2YrM2gz/2cbTHVy9x2PRfszirAET+2cYGKoTRV24ljyU7HG9xK1GRP4ZEzutovMdNB Q8iAW9Gyb4Idw4kbuZ6Spdvg3tmRkmG/fw0bRwDTJ2PB2ezdpVN6zg2Ai3ffdeqmJn ohoN62LQnFSgZNWlvfQhxetDcQEJiMeT5jZNEy1Y/J9FgsI7RepxHN0rv13TucMeTj f7ArJEztEEBnQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Nicholas Susanto , Charlene Liu , Zaeem Mohamed , Mark Broadworth , Alex Deucher , Sasha Levin , austin.zheng@amd.com, jun.lei@amd.com, harry.wentland@amd.com, sunpeng.li@amd.com, christian.koenig@amd.com, airlied@gmail.com, simona@ffwll.ch, Charlene.Liu@amd.com, chiahsuan.chung@amd.com, nicholas.kazlauskas@amd.com, paul.hsieh@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.12 31/37] drm/amd/display: Enable urgent latency adjustment on DCN35 Date: Tue, 29 Apr 2025 19:51:16 -0400 Message-Id: <20250429235122.537321-31-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250429235122.537321-1-sashal@kernel.org> References: <20250429235122.537321-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.12.25 Content-Transfer-Encoding: 8bit From: Nicholas Susanto [ Upstream commit 756c85e4d0ddc497b4ad5b1f41ad54e838e06188 ] [Why] Urgent latency adjustment was disabled on DCN35 due to issues with P0 enablement on some platforms. Without urgent latency, underflows occur when doing certain high timing configurations. After testing, we found that reenabling urgent latency didn't reintroduce p0 support on multiple platforms. [How] renable urgent latency on DCN35 and setting it to 3000 Mhz. This reverts commit 3412860cc4c0c484f53f91b371483e6e4440c3e5. Reviewed-by: Charlene Liu Signed-off-by: Nicholas Susanto Signed-off-by: Zaeem Mohamed Tested-by: Mark Broadworth Signed-off-by: Alex Deucher (cherry picked from commit cd74ce1f0cddffb3f36d0995d0f61e89f0010738) Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 47d785204f29c..beed7adbbd43e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -195,9 +195,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { .dcn_downspread_percent = 0.5, .gpuvm_min_page_size_bytes = 4096, .hostvm_min_page_size_bytes = 4096, - .do_urgent_latency_adjustment = 0, + .do_urgent_latency_adjustment = 1, .urgent_latency_adjustment_fabric_clock_component_us = 0, - .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, + .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, }; void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr) -- 2.39.5