[RFT PATCH 00/14] Add a single source of truth for UBWC configuration data

[Konrad Dybcio <konradybcio@kernel.org>]

As discussed a lot in the past, the UBWC config must be coherent across
a number of IP blocks (currently display and GPU, but it also may/will
concern camera/video as the drivers evolve).

So far, we've been trying to keep the values reasonable in each of the
two drivers separately, but it really make sense to do so, especially
given certain fields (see [1]) may need to be gathered dynamically.

This series introduces a Single Source of Truth (SSOT) database to be
consumed by multimedia drivers as needed.

[1] https://lore.kernel.org/linux-arm-msm/20250410-topic-smem_dramc-v2-0-dead15264714@oss.qualcomm.com/

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Konrad Dybcio (14):
      soc: qcom: Add UBWC config provider
      drm/msm: Use the central UBWC config database
      drm/msm/adreno: Offset the HBB value by 13
      drm/msm/a6xx: Get a handle to the common UBWC config
      drm/msm/a6xx: Resolve the meaning of AMSBC
      drm/msm/a6xx: Simplify uavflagprd_inv detection
      drm/msm/a6xx: Resolve the meaning of UBWC_MODE
      drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc
      drm/msm/a6xx: Resolve the meaning of rgb565_predicator
      drm/msm/a6xx: Stop tracking macrotile_mode (again)
      drm/msm/a6xx: Simplify min_acc_len calculation
      drm/msm/adreno: Switch to the common UBWC config struct
      drm/msm/a6xx: Drop cfg->ubwc_swizzle override
      drm/msm/a5xx: Use UBWC data from the common UBWC config struct

 drivers/gpu/drm/msm/Kconfig                        |   1 +
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c              |  17 +-
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c              | 129 ++++-----
 drivers/gpu/drm/msm/adreno/adreno_gpu.c            |  10 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h            |  41 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c        |   6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h        |   4 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h            |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          |   3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |   2 +-
 drivers/gpu/drm/msm/msm_mdss.c                     | 302 +++------------------
 drivers/soc/qcom/Kconfig                           |   8 +
 drivers/soc/qcom/Makefile                          |   1 +
 drivers/soc/qcom/ubwc_config.c                     | 255 +++++++++++++++++
 .../msm_mdss.h => include/linux/soc/qcom/ubwc.h    |  19 +-
 17 files changed, 395 insertions(+), 414 deletions(-)
---
base-commit: 19c541fe872387798a25df947f56a26212aa9a97
change-id: 20250430-topic-ubwc_central-53c540f019e5
prerequisite-message-id: <20250505-topic-7c3_rgb565pred_fix-v1-1-b1aebe890b8e@oss.qualcomm.com>
prerequisite-patch-id: b1d26d75633cacbde82a456bff06d27de2792733

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>