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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?xgehHeHGLygL3iMHXgRc5mIiD3nFW1PEq3W4hIVHQBb2pAwgKxh9hc3ysfKA?= =?us-ascii?Q?PlkXbREYToOp76n4HZi4qyewkCi5anj9jOZnl3ihZB1VJTFdo6CeYvwAzXTy?= =?us-ascii?Q?zAuGfH9HyNHRfV6GfdBwxNsUtPaDiWN0PUMAZi1iDhe/19bxNtcIGYuzlxUv?= =?us-ascii?Q?MeNf3nzdBzmDQcSOIpzXPSWqeQ+xTiYsx8STZ1+KwHP0FemgkdPmjmmdMaPO?= =?us-ascii?Q?bUnF/j+8SlBLoDFUn7lJDcutZjbgdRGAbb2jcLYOAbt1JQa2uDO8+fnJuPu8?= =?us-ascii?Q?FiD9dh44/6sQu+ia5RJWLl7fVuLvSUo3zqBf9qBSbqiadeiWP8mUZTG4+ifl?= =?us-ascii?Q?JSFftRw6xuqAiqn6HB7Mf3zur72xOpX9bi+v2nssIfIy5TAn8Vo2cP8D/Zqc?= =?us-ascii?Q?Qpt39DAbqxKl78lo9NzKeBVqfdWc8Ru1K2Jva62GsrlUMK0tMNCXjXBH2ZEU?= =?us-ascii?Q?kp20csVNAFBVY2lOnV8WT0gY+B4KMsTmbaW5S5JHVaLfpI665MZ2CAAo5P32?= =?us-ascii?Q?UYb3yVKN4nOGasmCjfpAXiw+2xfSCED1iNloQFEfur3HERafJJDArRLoP0ec?= =?us-ascii?Q?2Egvsk0a2EJraAqz2u7kS7sSl0PED7vHCZktsktvxml6BdalJaXHtcCXTTDC?= =?us-ascii?Q?vwFWoF3qHWb3VTbdnUzuxsbNSqgky//1Yzl4WSEyN/kBf1LwqM9ChsdP30zx?= =?us-ascii?Q?oW0XzXbdXuztausKYLJ7OQk/7iRkQx+mxWH1zexyiY39TriUl+OEpdPfXIyh?= =?us-ascii?Q?ddyk23CxzGo3v8W214sEuLvDU6c3SdOIH6cBpAROeT0TxNQbYVepOx72jANG?= =?us-ascii?Q?urhlCIjCxLbjy3SfF1h25BS6LDGt/jQp4fI+iY1R8RkaoYyHENMeCbt0wl+T?= =?us-ascii?Q?q6kNky07YleCklJYEWWQg/2nGH2U+K4ZM5ksPmKQk1nI6f7JT0WCvNtgmcom?= =?us-ascii?Q?jo6OhHcQFFpEQ3lXhlrN1gYZdNH/zgJs4EWDkY6x+6nt6QATz8sDAzh4TtZN?= =?us-ascii?Q?r9LHAANdVCKUdOVdcgjcifUvop+NbheJJT97cc61UoKwPyUsN+MxnrvtIgb9?= =?us-ascii?Q?xg2nCp/f7Z+ZAmB56feihxqAuOv/679XZVcncjXSiVRfxCANPgQInJX8htKn?= =?us-ascii?Q?YxuhGIFmHeVD4VFm84xEt6a04EOXpq+yZs3IktCeRLCYv5+nuIIhzsTVRRLk?= =?us-ascii?Q?leRSDJ9tgH9G4VWiamNYVBoAhAAPzQo3qmsyxdLapi7Iv9EONHEE6pD04k7M?= =?us-ascii?Q?DMfWr6Bil+ISUOM89S4ZN6epcyFShC0662Yj72wza51PcjIiwGsSI+huqWme?= =?us-ascii?Q?Zsa34sgXwUZboDrMP8HN7FOxOYyo6epm0AUf8cpRifGm4nd6eBxi9PL2zG82?= =?us-ascii?Q?HuIvtsHcWrIS5TBAPbVgSrw1QusNpxKfaGWkOa4OG9aZgI+b7Pdu/b+eA3IC?= =?us-ascii?Q?zRb/Me3YQhyXUQyoPt9urNlJizhZIEYInnRs/n3fR52yxX1UdJ2m6sRqGQBH?= =?us-ascii?Q?r5kEb12uPO6Rl5F2Qk/+BDLbnophd7np3FQoeYxPPba2gI/uSLMv/xBIhyD3?= =?us-ascii?Q?mj/6LZ2MTCxoRJuUYmk7rJEVUrFQd8QItW8zPsF8?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c563e11d-ff75-4f3d-7d82-08dd8e486d66 X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2025 15:53:08.3907 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6+0nkfKoJNsTdFVHCu69zhRkHI7ugrwWQrkneT2U4RIIEeZkb5q6zTQ4olvKo/e6hTFo3KbPf4SxCl6M2d+UgA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6599 On Wed, May 07, 2025 at 09:35:39PM +0200, Borislav Petkov wrote: > On Tue, Apr 15, 2025 at 02:55:09PM +0000, Yazen Ghannam wrote: > > -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) > > -{ > > - u32 low = 0, high = 0; > > - int def_offset = -1, def_new; > > - > > - if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) > > - return; > > - > > - def_new = (low & MASK_DEF_LVTOFF) >> 4; > > - if (!(low & MASK_DEF_LVTOFF)) { > > - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); > > I'm not sure why it is ok to remove that one. > > /me goes and digs into lore... > > Here's why we did it back then: > > https://lore.kernel.org/all/5547906E.3060701@amd.com/ > > and apparently that was for some bulldozer BIOS. > > How can we trust Zen BIOS all of a sudden? > > ;-) > Let me flip it around. Why is this check needed at all? Was there ever a real issue to resolve? It seems to me the deferred error updates are just following what other code did. I figure the reason to have the platform give the offset to the OS is so the OS doesn't hard code it (in case it needs to change). These offsets were hard coded in the past (conflict between IBS/THR), and it caused problems when the offsets switched in the hardware. The registers that give the offsets were introduced soon after, I think. So the checks we do are defeating the purpose. The OS is still hard coding the offsets. The goal of this change is to follow the intent of the design. Sometimes we need to let go and trust [the BIOS]. ;) Now we could update the checks to verify that an offset is not used for multiple interrupt sources. Let's follow up with the design folks to be sure. Thanks, Yazen