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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc8271aebsm104468735ad.107.2025.05.14.16.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 16:52:41 -0700 (PDT) From: Jessica Zhang Subject: [PATCH 0/5] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT Date: Wed, 14 May 2025 16:52:28 -0700 Message-Id: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIALwsJWgC/xWMSQqAMAwAvyI5G6hVcfmKeKgxag4upKKC9O/W4 zDMvOBZhT20yQvKl3jZtwhZmgAtbpsZZYwM1tjSFCbD1T24ysOKt4zngg3lZCwVNQ0VxOpQnqL +j10fwgf06RvzYQAAAA== X-Change-ID: 20250401-max-mixer-width-9c3c02c48cb7 To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Abhinav Kumar Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.15-dev-64971 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747266760; l=2865; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=sZUuOX2H5sa9Q5kPSygy9aJ3DncWNwsb4nZIr1PWjis=; b=2fS6E10p0+LUPEXfVUGN1EiKyx+7j+1YYXZmTcrfjwLs3yXOx0XYFA0FP7+b444XrmN0u80zg dX1gqwXcCIyAy5RdHn+91gwbPRhUbL6nNW3xP1GaSQ/v7obPx3VJ5Cw X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-GUID: tDt4SCdwKDicDJvTwsrGiaXYzbPb-46Q X-Proofpoint-ORIG-GUID: tDt4SCdwKDicDJvTwsrGiaXYzbPb-46Q X-Authority-Analysis: v=2.4 cv=cO7gskeN c=1 sm=1 tr=0 ts=68252cca cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=qDZEy-X_bfy3rWNFqZ0A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDIyMiBTYWx0ZWRfXzUctK8R4OXxv qJs+n4/a7ujAf+8f8cZ58SSm4zdTwcfFKCqlGfW86gGpe17FIFmfAIslR2Krz21tdVaPkM0kazl zQcOVqOUGhPl9wYS71KR0KuI8MAj3RsQRCP+mU29RMmsCfSeQBe0otZ2/fMbJiLeUncHpKLc7tU viKrbnkLMjwTHMKX/j6Dnt+Ogu+jBbWTi+8XCPEil5Vt80C3c+YWFXhYyXijHkvYtjUjky53FkT UclLb5EmgSZzAfzRVRvGTrIwtOfJaamakZ7oZiAniS4NonfHcElpD2xpu21oSlwjMteCfppSl1W R8sm5m/SRuGZywmF39U46YWzui80rYwhcykFqhTTwJI6xDC2Fsx/vd3zzXLmN9VkYVveDUV/Vb3 QpCsWq0iKhAJ9sQexqbF1lvuTOh/WWZZSlAx2v6NinCPJYwKSZM8UN6caZvtYBqcvhY1RlPm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=874 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140222 Currently, the DPU driver bases LM reservation off of the maximum supported width for the layer mixer and an arbitrary MAX_HDISPLAY_SPLIT. However, these limits are not hardware limits meaning that a single LM can support higher resolutions. Switch to basing LM reservation off of PINGPONG and DSC encoder hardware limits. --- Jessica Zhang (5): drm/msm/dpu: Drop maxwidth from dpu_lm_sub_blks struct drm/msm/dpu: Add max pingpong and dsc width to HW catalog drm/msm/dpu: Check mode against PINGPONG or DSC max width drm/msm/dpu: Filter writeback modes using writeback maxlinewidth drm/msm/dpu: Remove max_mixer_width from catalog .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 +++++- .../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 3 +- .../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 3 +- .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 5 ++- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 5 ++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 5 ++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 3 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 5 ++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +++- .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 5 ++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 4 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 3 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 3 +- .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 +++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 ++- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 +++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 10 ++++- .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 10 ++++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 10 ++++- .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 10 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 46 ++++++++++++++++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +---- 31 files changed, 173 insertions(+), 49 deletions(-) --- base-commit: 888f15dae780db7cea6ab1a3355151e4292038bf change-id: 20250401-max-mixer-width-9c3c02c48cb7 Best regards, -- Jessica Zhang