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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc8271aebsm104468735ad.107.2025.05.14.16.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 16:52:47 -0700 (PDT) From: Jessica Zhang Date: Wed, 14 May 2025 16:52:33 -0700 Subject: [PATCH 5/5] drm/msm/dpu: Remove max_mixer_width from catalog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250514-max-mixer-width-v1-5-c8ba0d9bb858@oss.qualcomm.com> References: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> In-Reply-To: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Abhinav Kumar Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.15-dev-64971 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747266760; l=17506; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=FR/UnX260/Vn2NQFCzJ2cky51dUA4u7bl7zZ9YB/KsI=; b=5wBSmSpRMWf2bCUYh0At2gpXO5rSk2pn8aZ9HFmsRshcMHbb9pV86YFbWjc7TsjwjYfCOBUlF B1LK4QtlSTKCY1zxvqmWKGnchvGIzdxzxqTTJ85YcZrS/7RxledDoxV X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-GUID: ZqeQbAgN8qHU3IVLl5hIPCZEV0XMcxz6 X-Proofpoint-ORIG-GUID: ZqeQbAgN8qHU3IVLl5hIPCZEV0XMcxz6 X-Authority-Analysis: v=2.4 cv=JszxrN4C c=1 sm=1 tr=0 ts=68252cd1 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=nedybW00AaWt5EjSzA4A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDIyMiBTYWx0ZWRfXzcpVARWBg1pE +O9TAytHnCQUYLwDCZOdsziyZVKPzB+9C7sm8b7efo6UY0EUXdluXZvXuIEipymOY61E2NLijLK YMc6aCKV6MlL5sIe3D6XkNVFtM03XqwuOaakG7RaiZLlXyJFCrdz+5rW/2/jSK860xyia7G5dFZ Lfyr8eoj99efkr4KcpWQOof8BpF+PeL5IhRNS+GjSwthWm+1RQ5ryPfvBMjE5W8GRQ+QP6jl6zy tpmrOM/hmNJp5gBxbvmbSifDQO35O2zzyOIZb5KhHY3AC9DmBP5HLxiKxdp/Vq9kKkOfWq0dcdi afgkCXWaGXQaxzWLzm0gNY40tXW/QqGNL3z/la/MikecZOiD/HK+QspzrlacHFCplAOXNyuMner yYBNmg9eeQFVHd5StSGRHz1xkg9pCVWaK7Z1PNg7AtRBxAu+P7/1zQeBlz1jV6YI5uuAyDIo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140222 Remove the now-unused max_mixer_width field from the HW catalog Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 28 files changed, 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 9db31591e27e..2f0f4cf07338 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -8,7 +8,6 @@ #define _DPU_10_0_SM8650_H static const struct dpu_caps sm8650_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index 4ac89cadf328..6c1bfd6b6ac9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -7,7 +7,6 @@ #define _DPU_1_14_MSM8937_H static const struct dpu_caps msm8937_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .max_linewidth = DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size = 40 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index dbd4129439a8..c00d45b8fb6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -7,7 +7,6 @@ #define _DPU_1_14_MSM8917_H static const struct dpu_caps msm8917_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .max_linewidth = DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size = 16 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index a93976f6167c..5c1383b31691 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -7,7 +7,6 @@ #define _DPU_1_16_MSM8953_H static const struct dpu_caps msm8953_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .max_linewidth = DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size = 40 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index e2e99504c715..5dcd1f81a4c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -9,7 +9,6 @@ #define _DPU_1_7_MSM8996_H static const struct dpu_caps msm8996_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 1bdffe168fb1..a283b4107f8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -8,7 +8,6 @@ #define _DPU_3_0_MSM8998_H static const struct dpu_caps msm8998_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 03f46a652449..0c8362befe62 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -7,7 +7,6 @@ #define _DPU_3_2_SDM660_H static const struct dpu_caps sdm660_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 011e98e6e7db..49b9bd52bf41 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -7,7 +7,6 @@ #define _DPU_3_3_SDM630_H static const struct dpu_caps sdm630_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 152fa5ea12dd..e35fbe0eb1db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -8,7 +8,6 @@ #define _DPU_4_0_SDM845_H static const struct dpu_caps sdm845_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 7f0754e47c2e..b55cc140aa88 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -8,7 +8,6 @@ #define _DPU_5_0_SM8150_H static const struct dpu_caps sm8150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 1a904b68950a..22bfd755d214 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -8,7 +8,6 @@ #define _DPU_5_1_SC8180X_H static const struct dpu_caps sc8180x_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 7c65f77a2c43..6ca54f2401d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -8,7 +8,6 @@ #define _DPU_5_2_SM7150_H static const struct dpu_caps sm7150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index f0539dd11dc8..2f21b01393b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -7,7 +7,6 @@ #define _DPU_5_3_SM6150_H static const struct dpu_caps sm6150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index a357567ad597..e5c5945a0385 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -9,7 +9,6 @@ #define _DPU_5_4_SM6125_H static const struct dpu_caps sm6125_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x6, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index c0bf1eba1eab..ba2b5dda1054 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -8,7 +8,6 @@ #define _DPU_6_0_SM8250_H static const struct dpu_caps sm8250_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index d004e7ee71fb..43c7f6794cb5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -8,7 +8,6 @@ #define _DPU_6_2_SC7180_H static const struct dpu_caps sc7180_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index b0659b55542f..7c2be386fc73 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -8,7 +8,6 @@ #define _DPU_6_3_SM6115_H static const struct dpu_caps sm6115_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index ae0196372f35..6c4531be116f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -9,7 +9,6 @@ #define _DPU_6_4_SM6350_H static const struct dpu_caps sm6350_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index d9bb18f11a49..b5f78064f761 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -8,7 +8,6 @@ #define _DPU_6_5_QCM2290_H static const struct dpu_caps qcm2290_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 8893b39e2ca3..0564f108db22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -9,7 +9,6 @@ #define _DPU_6_9_SM6375_H static const struct dpu_caps sm6375_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 6ded8b0309d9..31517c894a13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -8,7 +8,6 @@ #define _DPU_7_0_SM8350_H static const struct dpu_caps sm8350_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index e1512ff5945c..9c5bc570b754 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -8,7 +8,6 @@ #define _DPU_7_2_SC7280_H static const struct dpu_caps sc7280_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0x7, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 2a084ee071b9..f2fbff348d16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -8,7 +8,6 @@ #define _DPU_8_0_SC8280XP_H static const struct dpu_caps sc8280xp_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 11, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 2cb3966ee51f..5e9cb02602ae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -8,7 +8,6 @@ #define _DPU_8_1_SM8450_H static const struct dpu_caps sm8450_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 1135918e0a86..e3b332c313b3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -7,7 +7,6 @@ #define _DPU_8_4_SA8775P_H static const struct dpu_caps sa8775p_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 0516e75a3a16..a27a50da28d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -8,7 +8,6 @@ #define _DPU_9_0_SM8550_H static const struct dpu_caps sm8550_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 23d044e10c75..7d5b94408e69 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -7,7 +7,6 @@ #define _DPU_9_2_X1E80100_H static const struct dpu_caps x1e80100_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 194780905d29..f0534c0cd905 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -341,7 +341,6 @@ struct dpu_rotation_cfg { /** * struct dpu_caps - define DPU capabilities - * @max_mixer_width max layer mixer line width support. * @max_dsc_encoder_width max dsc encoder line width support * @max_mixer_blendstages max layer mixer blend stages or * supported z order @@ -355,7 +354,6 @@ struct dpu_rotation_cfg { * @max_vdeci_exp max vertical decimation supported (max is 2^value) */ struct dpu_caps { - u32 max_mixer_width; u32 max_dsc_encoder_width; u32 max_mixer_blendstages; bool has_src_split; -- 2.49.0