From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Deepak Gupta" <debug@rivosinc.com>,
"Atish Patra" <atishp@rivosinc.com>
Subject: [PATCH v7 04/14] riscv: sbi: add FWFT extension interface
Date: Thu, 15 May 2025 10:22:05 +0200 [thread overview]
Message-ID: <20250515082217.433227-5-cleger@rivosinc.com> (raw)
In-Reply-To: <20250515082217.433227-1-cleger@rivosinc.com>
This SBI extensions enables supervisor mode to control feature that are
under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp
DTE, etc). Add an interface to set local features for a specific cpu
mask as well as for the online cpu mask.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/sbi.h | 17 +++++++++++
arch/riscv/kernel/sbi.c | 57 ++++++++++++++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 0938f2a8d01b..341e74238aa0 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -503,6 +503,23 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
unsigned long asid);
long sbi_probe_extension(int ext);
+int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags);
+int sbi_fwft_set_cpumask(const cpumask_t *mask, u32 feature,
+ unsigned long value, unsigned long flags);
+/**
+ * sbi_fwft_set_online_cpus() - Set a feature on all online cpus
+ * @feature: The feature to be set
+ * @value: The feature value to be set
+ * @flags: FWFT feature set flags
+ *
+ * Return: 0 on success, appropriate linux error code otherwise.
+ */
+static inline int sbi_fwft_set_online_cpus(u32 feature, unsigned long value,
+ unsigned long flags)
+{
+ return sbi_fwft_set_cpumask(cpu_online_mask, feature, value, flags);
+}
+
/* Check if current SBI specification version is 0.1 or not */
static inline int sbi_spec_is_0_1(void)
{
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 1d44c35305a9..818efafdc8e9 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -299,6 +299,63 @@ static int __sbi_rfence_v02(int fid, const struct cpumask *cpu_mask,
return 0;
}
+struct fwft_set_req {
+ u32 feature;
+ unsigned long value;
+ unsigned long flags;
+ atomic_t error;
+};
+
+static void cpu_sbi_fwft_set(void *arg)
+{
+ struct fwft_set_req *req = arg;
+ int ret;
+
+ ret = sbi_fwft_set(req->feature, req->value, req->flags);
+ if (ret)
+ atomic_set(&req->error, ret);
+}
+
+/**
+ * sbi_fwft_set() - Set a feature on the local hart
+ * @feature: The feature ID to be set
+ * @value: The feature value to be set
+ * @flags: FWFT feature set flags
+ *
+ * Return: 0 on success, appropriate linux error code otherwise.
+ */
+int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags)
+{
+ return -EOPNOTSUPP;
+}
+
+/**
+ * sbi_fwft_set_cpumask() - Set a feature for the specified cpumask
+ * @mask: CPU mask of cpus that need the feature to be set
+ * @feature: The feature ID to be set
+ * @value: The feature value to be set
+ * @flags: FWFT feature set flags
+ *
+ * Return: 0 on success, appropriate linux error code otherwise.
+ */
+int sbi_fwft_set_cpumask(const cpumask_t *mask, u32 feature,
+ unsigned long value, unsigned long flags)
+{
+ struct fwft_set_req req = {
+ .feature = feature,
+ .value = value,
+ .flags = flags,
+ .error = ATOMIC_INIT(0),
+ };
+
+ if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT)
+ return -EINVAL;
+
+ on_each_cpu_mask(mask, cpu_sbi_fwft_set, &req, 1);
+
+ return atomic_read(&req.error);
+}
+
/**
* sbi_set_timer() - Program the timer for next timer event.
* @stime_value: The value after which next timer event should fire.
--
2.49.0
next prev parent reply other threads:[~2025-05-15 8:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 8:22 [PATCH v7 00/14] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-05-15 8:22 ` [PATCH v7 01/14] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-05-15 8:22 ` [PATCH v7 02/14] riscv: sbi: remove useless parenthesis Clément Léger
2025-05-15 8:22 ` [PATCH v7 03/14] riscv: sbi: add new SBI error mappings Clément Léger
2025-05-15 8:22 ` Clément Léger [this message]
2025-05-15 8:22 ` [PATCH v7 05/14] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-05-15 8:22 ` [PATCH v7 06/14] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-05-15 8:22 ` [PATCH v7 07/14] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-05-15 8:22 ` [PATCH v7 08/14] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-05-15 8:22 ` [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-05-19 23:32 ` Charlie Jenkins
2025-05-20 8:19 ` Clément Léger
2025-05-20 17:08 ` Charlie Jenkins
2025-05-22 6:49 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 10/14] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-05-15 8:22 ` [PATCH v7 11/14] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-05-15 8:22 ` [PATCH v7 12/14] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-05-15 8:22 ` [PATCH v7 13/14] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-05-15 8:22 ` [PATCH v7 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-05-16 23:57 ` Atish Patra
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