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Thu, 15 May 2025 17:35:12 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 15 May 2025 17:35:12 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v3 17/17] drm/mediatek: Add support for MT8196 multiple mmsys Date: Thu, 15 May 2025 17:34:29 +0800 Message-ID: <20250515093454.1729720-18-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com> References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Nancy Lin Add code to support MT8196 SOC Multi MMSYS Driver Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 119 ++++++++++++++++++++++++- 1 file changed, 115 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 1e49ca3fef80..229f84a4e59c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -193,6 +193,10 @@ static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { {0, DDP_COMPONENT_DSI0}, }; +static const struct mtk_drm_route mt8196_mtk_ddp_routes[] = { + {2, DDP_COMPONENT_DSI0}, +}; + static const unsigned int mt8192_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, @@ -231,6 +235,50 @@ static const unsigned int mt8195_mtk_ddp_ext[] = { DDP_COMPONENT_DP_INTF1, }; +static const unsigned int mt8196_mtk_ddp_ovl0_main[] = { + DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0, + DDP_COMPONENT_OVL0_DLO_ASYNC5, +}; + +static const unsigned int mt8196_mtk_ddp_disp0_main[] = { + DDP_COMPONENT_DLI_ASYNC0, + DDP_COMPONENT_DLO_ASYNC1, +}; + +static const unsigned int mt8196_mtk_ddp_disp1_main[] = { + DDP_COMPONENT_DLI_ASYNC21, + DDP_COMPONENT_DVO0, +}; + +static const unsigned int mt8196_mtk_ddp_ovl0_ext[] = { + DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1, + DDP_COMPONENT_OVL0_DLO_ASYNC6, +}; + +static const unsigned int mt8196_mtk_ddp_disp0_ext[] = { + DDP_COMPONENT_DLI_ASYNC1, + DDP_COMPONENT_DLO_ASYNC2, +}; + +static const unsigned int mt8196_mtk_ddp_disp1_ext[] = { + DDP_COMPONENT_DLI_ASYNC22, + DDP_COMPONENT_DP_INTF0, +}; + +static const unsigned int mt8196_mtk_ddp_ovl1_third[] = { + DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2, + DDP_COMPONENT_OVL1_DLO_ASYNC5, +}; + +static const unsigned int mt8196_mtk_ddp_disp0_third[] = { + DDP_COMPONENT_DLI_ASYNC8, + DDP_COMPONENT_DLO_ASYNC3, +}; + +static const unsigned int mt8196_mtk_ddp_disp1_third[] = { + DDP_COMPONENT_DLI_ASYNC23, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -327,8 +375,65 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .min_height = 1, }; -static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { - .mmsys_dev_num = 1, +static const struct mtk_mmsys_driver_data mt8196_dispsys0_driver_data = { + .main_path = mt8196_mtk_ddp_disp0_main, + .main_len = ARRAY_SIZE(mt8196_mtk_ddp_disp0_main), + .main_order = 1, + .ext_path = mt8196_mtk_ddp_disp0_ext, + .ext_len = ARRAY_SIZE(mt8196_mtk_ddp_disp0_ext), + .ext_order = 1, + .third_path = mt8196_mtk_ddp_disp0_third, + .third_len = ARRAY_SIZE(mt8196_mtk_ddp_disp0_third), + .third_order = 1, + .mmsys_id = DISPSYS0, + .mmsys_dev_num = 4, + .max_width = 8191, + .min_width = 2, /* 2-pixel align when ethdr is bypassed */ + .min_height = 1, +}; + +static const struct mtk_mmsys_driver_data mt8196_dispsys1_driver_data = { + .main_path = mt8196_mtk_ddp_disp1_main, + .main_len = ARRAY_SIZE(mt8196_mtk_ddp_disp1_main), + .main_order = 2, + .ext_path = mt8196_mtk_ddp_disp1_ext, + .ext_len = ARRAY_SIZE(mt8196_mtk_ddp_disp1_ext), + .ext_order = 2, + .third_path = mt8196_mtk_ddp_disp1_third, + .third_len = ARRAY_SIZE(mt8196_mtk_ddp_disp1_third), + .conn_routes = mt8196_mtk_ddp_routes, + .num_conn_routes = ARRAY_SIZE(mt8196_mtk_ddp_routes), + .third_order = 2, + .mmsys_id = DISPSYS1, + .mmsys_dev_num = 4, + .max_width = 8191, + .min_width = 2, /* 2-pixel align when ethdr is bypassed */ + .min_height = 1, +}; + +static const struct mtk_mmsys_driver_data mt8196_ovlsys0_driver_data = { + .main_path = mt8196_mtk_ddp_ovl0_main, + .main_len = ARRAY_SIZE(mt8196_mtk_ddp_ovl0_main), + .main_order = 0, + .ext_path = mt8196_mtk_ddp_ovl0_ext, + .ext_len = ARRAY_SIZE(mt8196_mtk_ddp_ovl0_ext), + .ext_order = 0, + .mmsys_id = OVLSYS0, + .mmsys_dev_num = 4, + .max_width = 8191, + .min_width = 2, /* 2-pixel align when ethdr is bypassed */ + .min_height = 1, +}; + +static const struct mtk_mmsys_driver_data mt8196_ovlsys1_driver_data = { + .third_path = mt8196_mtk_ddp_ovl1_third, + .third_len = ARRAY_SIZE(mt8196_mtk_ddp_ovl1_third), + .third_order = 0, + .mmsys_id = OVLSYS1, + .mmsys_dev_num = 4, + .max_width = 8191, + .min_width = 2, /* 2-pixel align when ethdr is bypassed */ + .min_height = 1, }; static const struct of_device_id mtk_drm_of_ids[] = { @@ -358,8 +463,14 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8195_vdosys0_driver_data}, { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data}, - { .compatible = "mediatek,mt8365-mmsys", - .data = &mt8365_mmsys_driver_data}, + { .compatible = "mediatek,mt8196-dispsys0", + .data = &mt8196_dispsys0_driver_data}, + { .compatible = "mediatek,mt8196-dispsys1", + .data = &mt8196_dispsys1_driver_data}, + { .compatible = "mediatek,mt8196-ovlsys0", + .data = &mt8196_ovlsys0_driver_data}, + { .compatible = "mediatek,mt8196-ovlsys1", + .data = &mt8196_ovlsys1_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); -- 2.45.2