From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B13B297B67; Thu, 15 May 2025 09:35:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747301710; cv=none; b=XJxQssPD3qUdHXR2ci0sfLdtEA6z3VWQ0e0f8sBOKOdFZJop3hd2uEKIOtMepE6OQT9dg+fRZbqQsC6KgMNF8md5bk2zgFCHLvVHR4RhUmjxVHRLV1rrU9eqmIM1FJ3/33oogUllwnVwub7IDVITvTe9dKBbr9inR5kcP805nCg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747301710; c=relaxed/simple; bh=8C8oUaBih0po+klrzUBaNUVVUr2AubFq/9gEkDoAi7c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Cl2a7ictF5TWw5CS2E+ZhMbLhH6ty0FwlGfmaSG7VdwjQitQOIuNVmKU5uKw6z//t95FpdPv53cxm6ksAU6QWdD8fZpoUFYplfysqHGyZ9SWVB6WCbuZ0RR8Wrd6peAk23cs05kT65YK9a8H5ZXYX4fNrz6M8yn+fsENWPHYf+8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Xn6iv1pF; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Xn6iv1pF" X-UUID: e16e2598316f11f082f7f7ac98dee637-20250515 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=j2J5l+xRbE31jgtqUwEDN8zj3JwEqHj0EOYwVHDuBI8=; b=Xn6iv1pFbxfq/6UhNEPurDaPFOe9s1SFGb27hhuQJ69s+9a7lZWmsWpNU+NVaz4pwjPx7MHski58NYLbBVUEoMcOFW1umF1R9SH03JyfGnpN/22jbCeJ0iAG6A252Vtbix1HwxWwS87fzdddq35Ka/dJ3z+eF2ntCl7GpK3wAjs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:b47f9045-d795-4dfd-8502-fe78e4c3e150,IP:0,UR L:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:20 X-CID-META: VersionHash:0ef645f,CLOUDID:29e504c0-eade-4d5b-9f81-31d7b5452436,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|97|99|83|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: e16e2598316f11f082f7f7ac98dee637-20250515 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 593301339; Thu, 15 May 2025 17:35:04 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 15 May 2025 17:35:02 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 15 May 2025 17:35:02 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v3 04/17] dt-bindings: display: mediatek: add OUTPROC yaml for MT8196 Date: Thu, 15 May 2025 17:34:16 +0800 Message-ID: <20250515093454.1729720-5-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com> References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Paul-pl Chen Add mediate,outproc.yaml to support OUTPROC for MT8196. MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC,handles the post-stage of pixel processing in the overlapping procedure. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- .../display/mediatek/mediatek,outproc.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml new file mode 100644 index 000000000000..1292e394faaa --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap output processor + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC, + handles the post-stage of pixel processing in the overlapping procedure. + OVL_OUTPROC manages pixels for gamma correction and ensures that pixel + values are within the correct range. + +properties: + compatible: + const: mediatek,mt8196-outproc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + outproc0: outproc@32970000 { + compatible = "mediatek,mt8196-outproc"; + reg = <0 0x32970000 0 0x1000>; + clocks = <&ovlsys_config_clk 49>; + interrupts = ; + }; + }; -- 2.45.2