From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF15B1E47AD for ; Thu, 15 May 2025 13:48:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747316898; cv=none; b=B60pKH2l/aC4bc2Jrw7uDAnDVdSdZDn+BP31MSYwj1LIzIe0jZP7rt9HkNolsb7zjASf1xMHD6vXy40lZeifxTdZT4A5syArcBxTmr4vdcXtQgFKKsnWIsI5nPVJrMb4btpaRUknHc6qyk4aKIdFMXQ4qUv9HwCc4JWnDC488TA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747316898; c=relaxed/simple; bh=JDT4QS/B8QAOybBDqnsQFipQES9Aijnj7bUkwOXK0Sk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QW9b7ZEX/jtgOgzsFxrJwSy3xpsqT1THAyCb5SjaylpYlDJW9hFMhoTt76yI7d5HSfwNTq6N2fWRMou8EapA5VlRPocIC9I6qNU7HEIeApGDe0qjvWHdSOmvhsbqPgYo1THJFYIeP80N+HJPQdrDhmBm+UaDU2sbWYBqHOWsPTo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=k+A0O1hl; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k+A0O1hl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747316897; x=1778852897; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JDT4QS/B8QAOybBDqnsQFipQES9Aijnj7bUkwOXK0Sk=; b=k+A0O1hltzISXz3NyvHHidEXHIsn+phxLaXpg8/gnD5100bxkGwMnbCh IA2iL4JZOl3/CcXu0H+wx3t6+FOMXqE4ay+94hx3Bxg4G9Tf0s86C3V/Z NYeiAahcyKdkviEDkWo1Wk9TMq+/hIjP+FX98hwO/jQCUa1OCKJfUz/3Y p0u/PuK9EbjTzJm42ZfHeGhm4nTQHcZEHaWu1aIol7IP+kUdU59KZ5lzN I9bcDhHwMh7GF9uIapDgMkZjzl2u9GqoWuMqK67m9D/NU+hPR91ft0IZe qVsbOC6ZtbcQ2fYphX/q9ZFksPteGIgoeyNwwg5CS2gut6/8ClGx2wfio g==; X-CSE-ConnectionGUID: j+nhI8BnSF+6vV/dkZopCw== X-CSE-MsgGUID: pUSrv4uPTuKQe8MCNiw4cQ== X-IronPort-AV: E=McAfee;i="6700,10204,11434"; a="66660772" X-IronPort-AV: E=Sophos;i="6.15,291,1739865600"; d="scan'208";a="66660772" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2025 06:48:17 -0700 X-CSE-ConnectionGUID: aLtepNGDTJWmwwiVq1vz5Q== X-CSE-MsgGUID: nQZQhm4XTveYHLZCbHbskQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,291,1739865600"; d="scan'208";a="138428332" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2025 06:48:11 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa , Raag Jadav Cc: Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v10 05/10] mtd: intel-dg: align 64bit read and write Date: Thu, 15 May 2025 16:33:40 +0300 Message-ID: <20250515133345.2805031-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515133345.2805031-1-alexander.usyskin@intel.com> References: <20250515133345.2805031-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit GSC NVM controller HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Acked-by: Miquel Raynal Signed-off-by: Alexander Usyskin --- drivers/mtd/devices/mtd_intel_dg.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_intel_dg.c index eedc0974bb5b..2f32ed311ffd 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -246,6 +246,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, len_s -= to_shift; } + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + idg_nvm_write32(nvm, to, data); + if (idg_nvm_error(nvm)) + return -EIO; + buf += sizeof(u32); + to += sizeof(u32); + len_s -= sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data; @@ -303,6 +321,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region, from += from_shift; } + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data = idg_nvm_read32(nvm, from); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -= sizeof(u32); + buf += sizeof(u32); + from += sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data = idg_nvm_read64(nvm, from + i); -- 2.43.0