From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C3BD1A8F8A for ; Thu, 15 May 2025 13:48:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747316909; cv=none; b=Twu0fdJ6dGwk9LsBcPQQa0etlHUJK1amIfm2ZgF8CNH7ZufsjWfOuAXBUhg5eby2V4vq3HL450ZSdhPNxCbX2jK8SE1o61iZuhdfiBH5MoVxdt+XU2IKpkLIVcFC26zOG3h7wS2/PEpww1/zjeclUyeZuB15Pva5n5nELQRMqgI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747316909; c=relaxed/simple; bh=lBZ2ULNOwanm8+4z0E89ucXzMn5Qz+pSLa83A9usEGo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BzyHRmAtrF1GbYMf8zIv/9ZuBBay0lrsWifOHjMCp9FzVQTCVoGhzHJdiCSFg4GQ2Z81+e2HegL29Ssi1olwO4buATiqiZ4RzNDXn3Jt73XSdE2ESE9XgBLHbDfxZ4fK6KHkp8MAm7kDHc/wpSGiXUImhLEicz/H9jgE9embCLc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ymby3nUM; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ymby3nUM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747316909; x=1778852909; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lBZ2ULNOwanm8+4z0E89ucXzMn5Qz+pSLa83A9usEGo=; b=Ymby3nUMJe17UPf/KXseHJmJGy2nZfbbeaujHdjEjp26n8RVzDyo3JxJ tFcz7LPd8oPDfjYkTbSGH9mnM93ekLksVlDRRUz9jraPhpZDMKg93ooP9 2QbdUyrf5gq/1LnVV8sJkoysOJhTPHGQs+Hj/K7ZqAKj4wlJ7I21PL6UU gqtuISZ3KQhNSYAEVO16IAIOMfS4I/H1RnIUSy9ug5I2Sv8C3QmhCbdiV ZYP9AONFlEFcsAXFPZZ7wzvcviUbqpKo0kiSQsQBAxl34WoLX2O68AbCo OEwOWjlKElmOAslYSpvzlvP26YEyDzLFH4uTg1pw1yZUw3JT5PujHXUZ2 g==; X-CSE-ConnectionGUID: clYn/IMwS0+vCJwTV6tssw== X-CSE-MsgGUID: yYWyZMouRoeJmvSVrQt3KQ== X-IronPort-AV: E=McAfee;i="6700,10204,11434"; a="66660834" X-IronPort-AV: E=Sophos;i="6.15,291,1739865600"; d="scan'208";a="66660834" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2025 06:48:28 -0700 X-CSE-ConnectionGUID: bLNDiCe9S3SgwADdVlfwGw== X-CSE-MsgGUID: L93tc7/rTySqno/gi/h2kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,291,1739865600"; d="scan'208";a="138428352" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2025 06:48:22 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa , Raag Jadav Cc: Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v10 07/10] drm/i915/nvm: add support for access mode Date: Thu, 15 May 2025 16:33:42 +0300 Message-ID: <20250515133345.2805031-8-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515133345.2805031-1-alexander.usyskin@intel.com> References: <20250515133345.2805031-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_nvm.c index 75d3ebe669ff..dd3999c934a7 100644 --- a/drivers/gpu/drm/i915/intel_nvm.c +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -10,6 +10,7 @@ #include "intel_nvm.h" #define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = { [0] = { .name = "DESCRIPTOR", }, @@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev) { } +static bool i915_nvm_writable_override(struct drm_i915_private *i915) +{ + resource_size_t base; + bool writable_override; + + if (IS_DG1(i915)) { + base = DG1_GSC_HECI2_BASE; + } else if (IS_DG2(i915)) { + base = DG2_GSC_HECI2_BASE; + } else { + drm_err(&i915->drm, "Unknown platform\n"); + return true; + } + + writable_override = + !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writable_override) + drm_info(&i915->drm, "NVM access overridden by jumper\n"); + return writable_override; +} + void intel_nvm_init(struct drm_i915_private *i915) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); @@ -43,7 +66,7 @@ void intel_nvm_init(struct drm_i915_private *i915) nvm = i915->nvm; - nvm->writeable_override = true; + nvm->writable_override = i915_nvm_writable_override(i915); nvm->bar.parent = &pdev->resource[0]; nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; -- 2.43.0