From: Ard Biesheuvel <ardb+git@google.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Ingo Molnar <mingo@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Brian Gerst <brgerst@gmail.com>,
"Kirill A. Shutemov" <kirill@shutemov.name>
Subject: [PATCH v4 3/6] x86/cpu: Allow caps to be set arbitrarily early
Date: Sat, 17 May 2025 11:16:43 +0200 [thread overview]
Message-ID: <20250517091639.3807875-11-ardb+git@google.com> (raw)
In-Reply-To: <20250517091639.3807875-8-ardb+git@google.com>
From: Ard Biesheuvel <ardb@kernel.org>
cpu_feature_enabled() uses a ternary alternative, where the late variant
is based on code patching and the early variant accesses the capability
field in boot_cpu_data directly.
This allows cpu_feature_enabled() to be called quite early, but it still
requires that the CPU feature detection code runs before being able to
rely on the return value of cpu_feature_enabled().
This is a problem for the implementation of pgtable_l5_enabled(), which
is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be
called extremely early. Currently, there is a hacky workaround where
some source files that may execute before (but also after) CPU feature
detection have a different version of pgtable_l5_enabled(), based on the
USE_EARLY_PGTABLE_L5 preprocessor macro.
Instead, let's make it possible to set CPU feature arbitrarily early, so
that the X86_FEATURE_5LEVEL_PAGING capability can be set before even
entering C code, by making sure that boot_cpu_data.x86_capability[] is
not [redundantly] wiped again when detecting CPU features.
Note that forcing a capability requires setting it in cpu_caps_set[]
too, which has been moved out of BSS in a preceding patch.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/x86/kernel/cpu/common.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 579d5b84e183..7392a75d85c3 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1708,9 +1708,6 @@ static void __init cpu_parse_early_param(void)
*/
static void __init early_identify_cpu(struct cpuinfo_x86 *c)
{
- memset(&c->x86_capability, 0, sizeof(c->x86_capability));
- c->extended_cpuid_level = 0;
-
if (!cpuid_feature())
identify_cpu_without_cpuid(c);
@@ -1922,7 +1919,6 @@ static void identify_cpu(struct cpuinfo_x86 *c)
c->x86_virt_bits = 32;
#endif
c->x86_cache_alignment = c->x86_clflush_size;
- memset(&c->x86_capability, 0, sizeof(c->x86_capability));
#ifdef CONFIG_X86_VMX_FEATURE_NAMES
memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
#endif
@@ -2084,6 +2080,7 @@ void identify_secondary_cpu(unsigned int cpu)
*c = boot_cpu_data;
c->cpu_index = cpu;
+ memset(&c->x86_capability, 0, sizeof(c->x86_capability));
identify_cpu(c);
#ifdef CONFIG_X86_32
enable_sep_cpu();
--
2.49.0.1101.gccaa498523-goog
next prev parent reply other threads:[~2025-05-17 9:16 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-17 9:16 [PATCH v4 0/6] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-17 14:28 ` Ard Biesheuvel
2025-05-19 8:35 ` Ingo Molnar
2025-05-19 9:40 ` Borislav Petkov
2025-05-19 9:46 ` Ard Biesheuvel
2025-05-19 12:15 ` Borislav Petkov
2025-05-19 12:24 ` Borislav Petkov
2025-05-19 12:25 ` Ard Biesheuvel
2025-05-19 13:08 ` Ingo Molnar
2025-05-19 13:19 ` Borislav Petkov
2025-05-21 15:23 ` Thomas Gleixner
2025-05-21 18:11 ` Borislav Petkov
2025-05-21 18:56 ` Thomas Gleixner
2025-05-21 19:29 ` Borislav Petkov
2025-05-21 19:41 ` Thomas Gleixner
2025-05-21 19:48 ` Borislav Petkov
2025-05-21 20:07 ` Thomas Gleixner
2025-05-22 7:55 ` Peter Zijlstra
2025-05-22 15:08 ` Sean Christopherson
2025-05-22 19:58 ` Thomas Gleixner
2025-05-22 22:15 ` Sean Christopherson
2025-05-19 12:55 ` [tip: x86/core] x86/cpu: Use a new feature flag for 5-level paging tip-bot2 for Ard Biesheuvel
2025-05-19 13:12 ` Ingo Molnar
2025-05-17 9:16 ` [PATCH v4 2/6] x86/cpu: Move CPU capability override arrays from BSS to __ro_after_init Ard Biesheuvel
2025-05-19 12:01 ` Brian Gerst
2025-05-17 9:16 ` Ard Biesheuvel [this message]
2025-05-17 9:16 ` [PATCH v4 4/6] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 5/6] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 6/6] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel
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