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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECD4.mail.protection.outlook.com (10.167.242.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8769.18 via Frontend Transport; Mon, 19 May 2025 03:42:54 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 18 May 2025 22:40:01 -0500 From: Nava kishore Manne To: , , , , , , , , , Subject: [RFC v3 0/1]Add user space interaction for FPGA programming Date: Mon, 19 May 2025 09:09:36 +0530 Message-ID: <20250519033950.2669858-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="N" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD4:EE_|PH8PR12MB6722:EE_ X-MS-Office365-Filtering-Correlation-Id: ef490fb7-98b2-4480-7800-08dd96873d1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013|921020|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2025 03:42:54.5936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef490fb7-98b2-4480-7800-08dd96873d1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6722 The existing FPGA manager subsystem didn't have any user space interface (other than the status/state in sysfs) in Kernel. Basically, FPGAs are semiconductor devices that can be reprogrammed for desired hardware functionality. FPGAs can be reprogrammed at runtime with different types of logic and IPs as per user need and hence there is a need to use device tree overlays for removing/updating/adding the devices at runtime for the IPs/controllers that are present in FPGA. But we don't have any user interface in kernel for updating the device tree at runtime. Sometime back there was a series sent by Pantelis Antoniou (https://lore.kernel.org/lkml/1414528565-10907-4-git-send-email-pantelis.antoniou@konsulko.com/). This patch introduced a user interface configfs for Device Tree overlays, a method of dynamically altering the kernel's live Device Tree. However, this patch series was not accepted in mainline due to various concerns. For more details refer to this link: https://elinux.org/Frank%27s_Evolving_Overlay_Thoughts#issues_and_what_needs_to_be_completed_--_Not_an_exhaustive_list One of the major valid concerns that were raised with this configfs interface was security. It provides a generic interface (Not specific to the use cases) for modifying the live device tree. In order to configure/program the FPGA devices, All the major vendors of FPGA are using this configfs series as out-of-tree patch for configuring the FPGAs and there was never an attempt to introduce a generic interface to configure/program the FPGA in upstream and hence upstream kernel ended up in not having proper support for FPGAs configure/program. This series tries to address this gap of FPGA programmability by providing a new ConfigFS-based interface to the user. The newly introduced ConfigFS interface offers a generic and standardized mechanism for configuring or reprogramming FPGAs at runtime. It supports both Open Firmware (OF) and non-OF devices, utilizing vendor-specific callbacks—such as pre_config, post_config, removal, and status checks. To accommodate diverse device-specific configurations. This solution enhances FPGA runtime management, supporting various device types and vendors, while ensuring compatibility with the current FPGA configuration flow. Nava kishore Manne (1): fpga-region: Introduce ConfigFS interface for runtime FPGA configuration drivers/fpga/fpga-region.c | 196 +++++++++++++ drivers/fpga/of-fpga-region.c | 474 +++++++++++++++++-------------- include/linux/fpga/fpga-region.h | 34 +++ 3 files changed, 493 insertions(+), 211 deletions(-) -- 2.43.0