From: Geetha sowjanya <gakula@marvell.com>
To: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <kuba@kernel.org>, <davem@davemloft.net>, <pabeni@redhat.com>,
<edumazet@google.com>, <andrew+netdev@lunn.ch>,
<sgoutham@marvell.com>, <gakula@marvell.com>,
<sbhatta@marvell.com>, <hkelam@marvell.com>
Subject: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table entries
Date: Wed, 21 May 2025 11:38:33 +0530 [thread overview]
Message-ID: <20250521060834.19780-2-gakula@marvell.com> (raw)
In-Reply-To: <20250521060834.19780-1-gakula@marvell.com>
From: Subbaraya Sundeep <sbhatta@marvell.com>
This patch enables the LMT line for a PF/VF by setting the
LMT_ENA bit in the APR_LMT_MAP_ENTRY_S structure.
Additionally, it simplifies the logic for calculating the
LMTST table index by consistently using the maximum
number of hw supported VFs (i.e., 256).
Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table").
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
.../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
index 7fa98aeb3663..3838c04b78c2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
@@ -15,13 +15,17 @@
#define LMT_TBL_OP_WRITE 1
#define LMT_MAP_TABLE_SIZE (128 * 1024)
#define LMT_MAPTBL_ENTRY_SIZE 16
+#define LMT_MAX_VFS 256
+
+#define LMT_MAP_ENTRY_ENA BIT_ULL(20)
+#define LMT_MAP_ENTRY_LINES GENMASK_ULL(18, 16)
/* Function to perform operations (read/write) on lmtst map table */
static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
int lmt_tbl_op)
{
void __iomem *lmt_map_base;
- u64 tbl_base;
+ u64 tbl_base, cfg;
tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
@@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
*val = readq(lmt_map_base + index);
} else {
writeq((*val), (lmt_map_base + index));
+
+ cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
+ /* 2048 LMTLINES */
+ cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
+
+ writeq(cfg, (lmt_map_base + (index + 8)));
+
/* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
* changes effective. Write 1 for flush and read is being used as a
* barrier and sets up a data dependency. Write to 0 after a write
@@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
#define LMT_MAP_TBL_W1_OFF 8
static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
{
- return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
+ return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) +
(pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;
}
--
2.25.1
next prev parent reply other threads:[~2025-05-21 6:08 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-21 6:08 [net PATCH 0/2] octeontx2-af: APR Mapping Fixes Geetha sowjanya
2025-05-21 6:08 ` Geetha sowjanya [this message]
2025-05-21 8:39 ` [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table entries Michal Swiatkowski
2025-05-21 12:00 ` Geethasowjanya Akula
2025-05-21 6:08 ` [net PATCH 2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG Geetha sowjanya
2025-05-21 8:36 ` Michal Swiatkowski
2025-05-21 12:07 ` Geethasowjanya Akula
2025-05-22 10:15 ` Paolo Abeni
2025-05-22 10:40 ` [net PATCH 0/2] octeontx2-af: APR Mapping Fixes patchwork-bot+netdevbpf
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