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[142.167.56.70]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6fac6e00dcfsm23235216d6.87.2025.05.30.07.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 07:14:20 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1uL0V1-00000001ELN-1sQe; Fri, 30 May 2025 11:14:19 -0300 Date: Fri, 30 May 2025 11:14:19 -0300 From: Jason Gunthorpe To: Alexandre Courbot Cc: Abdiel Janulgue , dakr@kernel.org, lyude@redhat.com, Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?B?QmrDtnJu?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Valentin Obst , open list , Marek Szyprowski , Robin Murphy , airlied@redhat.com, rust-for-linux@vger.kernel.org, "open list:DMA MAPPING HELPERS" , Petr Tesarik , Andrew Morton , Herbert Xu , Sui Jingfeng , Randy Dunlap , Michael Kelley Subject: Re: [PATCH 1/2] rust: add initial scatterlist bindings Message-ID: <20250530141419.GA292183@ziepe.ca> References: <20250528221525.1705117-1-abdiel.janulgue@gmail.com> <20250528221525.1705117-2-abdiel.janulgue@gmail.com> <20250529004550.GB192517@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, May 30, 2025 at 11:02:02PM +0900, Alexandre Courbot wrote: > You would have a trait for providing the pages and their range: > > /// Provides a list of pages that can be used to build a `SGTable`. > trait SGTablePages { > /// Returns an iterator to the pages providing the backing memory of `self`. > fn pages_iter<'a>(&'a self) -> impl Iterator; > /// Returns the effective range of the mapping. > fn range(&self) -> Range; > } > > The `SGTable` becomes something like: > > struct SGTable > { > table: Opaque, > pages: P, > _s: PhantomData, > } At this point it isn't exactly a sgtable anymore, it is some rust specific way to get a dma mapped scatterlist. Most of the actual ways to use a sgtable's cpu side would become unavailable for safety reasons. That seems fine to me, and is what I was suggesting when I said not to expose set_page at all. But I would maybe lean into it a bit more, why have the type state at all anymore if the flow is SGTablePages -> SgTable -> Dma Mapped? There isn't really a reason to expose the CPU populated but not yet mapped state to the user at all. They can't do anything with it. Just directly create the DMA mapped scatterlist and only expose the DMA list through the rust API in a single step. So much simpler to understand and doesn't leak the bad decisions of the scatterlist design. Certainly the initial uses of scatterlist don't need to ever know about or touch the CPU side of the scatterlist, and it would be great if Rust could stay that way.. Jason