drivers/clocksource/timer-tegra186.c:282: undefined reference to `__udivdi3'

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   0f70f5b08a47a3bc1a252e5f451a137cde7c98ce
commit: 28c842c8b0f5d1c2da823b11326e63cdfdbc3def clocksource/drivers/timer-tegra186: Add WDIOC_GETTIMELEFT support
date:   2 weeks ago
config: i386-buildonly-randconfig-2002-20250531 (https://download.01.org/0day-ci/archive/20250531/202505312203.NmHWLzpj-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250531/202505312203.NmHWLzpj-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505312203.NmHWLzpj-lkp@intel.com/

All errors (new ones prefixed by >>):

   ld: drivers/clocksource/timer-tegra186.o: in function `tegra186_wdt_get_timeleft':
>> drivers/clocksource/timer-tegra186.c:282: undefined reference to `__udivdi3'


vim +282 drivers/clocksource/timer-tegra186.c

   241	
   242	static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd)
   243	{
   244		struct tegra186_wdt *wdt = to_tegra186_wdt(wdd);
   245		u32 expiration, val;
   246		u64 timeleft;
   247	
   248		if (!watchdog_active(&wdt->base)) {
   249			/* return zero if the watchdog timer is not activated. */
   250			return 0;
   251		}
   252	
   253		/*
   254		 * Reset occurs on the fifth expiration of the
   255		 * watchdog timer and so when the watchdog timer is configured,
   256		 * the actual value programmed into the counter is 1/5 of the
   257		 * timeout value. Once the counter reaches 0, expiration count
   258		 * will be increased by 1 and the down counter restarts.
   259		 * Hence to get the time left before system reset we must
   260		 * combine 2 parts:
   261		 * 1. value of the current down counter
   262		 * 2. (number of counter expirations remaining) * (timeout/5)
   263		 */
   264	
   265		/* Get the current number of counter expirations. Should be a
   266		 * value between 0 and 4
   267		 */
   268		val = readl_relaxed(wdt->regs + WDTSR);
   269		expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, val);
   270		if (WARN_ON_ONCE(expiration > 4))
   271			return 0;
   272	
   273		/* Get the current counter value in microsecond. */
   274		val = readl_relaxed(wdt->tmr->regs + TMRSR);
   275		timeleft = FIELD_GET(TMRSR_PCV, val);
   276	
   277		/*
   278		 * Calculate the time remaining by adding the time for the
   279		 * counter value to the time of the counter expirations that
   280		 * remain.
   281		 */
 > 282		timeleft += (((u64)wdt->base.timeout * USEC_PER_SEC) / 5) * (4 - expiration);
   283	
   284		/*
   285		 * Convert the current counter value to seconds,
   286		 * rounding up to the nearest second. Cast u64 to
   287		 * u32 under the assumption that no overflow happens
   288		 * when coverting to seconds.
   289		 */
   290		timeleft = DIV_ROUND_CLOSEST_ULL(timeleft, USEC_PER_SEC);
   291	
   292		if (WARN_ON_ONCE(timeleft > U32_MAX))
   293			return U32_MAX;
   294	
   295		return lower_32_bits(timeleft);
   296	}
   297	

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