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Tue, 03 Jun 2025 11:04:23 -0700 (PDT) Received: from qasdev.Home ([2a02:c7c:6696:8300:397c:823b:f900:56d9]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4efe5b887sm19468210f8f.18.2025.06.03.11.04.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 11:04:22 -0700 (PDT) From: Qasim Ijaz To: lucas.demarchi@intel.com, thomas.hellstrom@linux.intel.com, rodrigo.vivi@intel.com, airlied@gmail.com, simona@ffwll.ch Cc: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/xe/hwmon: fix uninitialised access in xe_hwmon_pcode_write_power_limit Date: Tue, 3 Jun 2025 19:03:33 +0100 Message-Id: <20250603180333.32117-1-qasdev00@gmail.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=n Content-Transfer-Encoding: 8bit val0/val1 are not initialised and are passed to xe_pcode_read(): xe_hwmon_pcode_write_power_limit() └─▶ xe_pcode_read() └─▶ pcode_mailbox_rw() └─▶ __pcode_mailbox_rw() If __pcode_mailbox_rw fails, val0/val1 could be left uninitialised leading to xe_hwmon_pcode_write_power_limit() to access them via drm_dbg. Or an uninitialised val0/val1 could be dereferenced inside __pcode_mailbox_rw. To fix zero-initialise them to avoid potential UB and propagate error on failure. Fixes: 7596d839f622 ("drm/xe/hwmon: Add support to manage power limits though mailbox") Signed-off-by: Qasim Ijaz --- drivers/gpu/drm/xe/xe_hwmon.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c index 0d32e977537c..04acb47488a0 100644 --- a/drivers/gpu/drm/xe/xe_hwmon.c +++ b/drivers/gpu/drm/xe/xe_hwmon.c @@ -179,7 +179,7 @@ static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 at u32 uval) { struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); - u32 val0, val1; + u32 val0 = 0, val1 = 0; int ret = 0; ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, @@ -190,9 +190,11 @@ static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 at READ_PL_FROM_PCODE : READ_PL_FROM_FW), &val0, &val1); - if (ret) + if (ret) { drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", channel, val0, val1, ret); + return ret; + } if (attr == PL1_HWMON_ATTR) val0 = uval; -- 2.39.5