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From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: "Rob Herring (Arm)" <robh@kernel.org>
Cc: Michael Kelley <mhklinux@outlook.com>,
	linux-acpi@vger.kernel.org, Wei Liu <wei.liu@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Yunhong Jiang <yunhong.jiang@linux.intel.com>,
	"K. Y. Srinivasan" <kys@microsoft.com>,
	Chris Oo <cho@microsoft.com>,
	Ricardo Neri <ricardo.neri@intel.com>,
	linux-hyperv@vger.kernel.org,
	Haiyang Zhang <haiyangz@microsoft.com>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	linux-kernel@vger.kernel.org,
	"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	x86@kernel.org, Saurabh Sengar <ssengar@linux.microsoft.com>,
	Dexuan Cui <decui@microsoft.com>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v4 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors
Date: Wed, 4 Jun 2025 08:17:20 -0700	[thread overview]
Message-ID: <20250604151720.GC29325@ranerica-svr.sc.intel.com> (raw)
In-Reply-To: <174900070284.2624702.4580450009482590306.robh@kernel.org>

On Tue, Jun 03, 2025 at 08:31:42PM -0500, Rob Herring (Arm) wrote:
> 
> On Tue, 03 Jun 2025 17:15:15 -0700, Ricardo Neri wrote:
> > Add DeviceTree bindings to enumerate the wakeup mailbox used in platform
> > firmware for Intel processors.
> > 
> > x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert
> > followed by Start-Up IPI messages. The wakeup mailbox can be used when this
> > mechanism is unavailable.
> > 
> > The wakeup mailbox offers more control to the operating system to boot
> > secondary CPUs than a spin-table. It allows the reuse of same wakeup vector
> > for all CPUs while maintaining control over which CPUs to boot and when.
> > While it is possible to achieve the same level of control using a spin-
> > table, it would require to specify a separate `cpu-release-addr` for each
> > secondary CPU.
> > 
> > The operation and structure of the mailbox is described in the
> > Multiprocessor Wakeup Structure defined in the ACPI specification. Note
> > that this structure does not specify how to publish the mailbox to the
> > operating system (ACPI-based platform firmware uses a separate table). No
> > ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox.
> > 
> > Add a `compatible` property that the operating system can use to discover
> > the mailbox. Nodes wanting to refer to the reserved memory usually define a
> > `memory-region` property. /cpus/cpu* nodes would want to refer to the
> > mailbox, but they do not have such property defined in the DeviceTree
> > specification. Moreover, it would imply that there is a memory region per
> > CPU.
> > 
> > Co-developed-by: Yunhong Jiang <yunhong.jiang@linux.intel.com>
> > Signed-off-by: Yunhong Jiang <yunhong.jiang@linux.intel.com>
> > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
> > ---
> > Changes since v3:
> >  - Removed redefinitions of the mailbox and instead referred to ACPI
> >    specification as per discussion on LKML.
> >  - Clarified that DeviceTree-based firmware do not require the use of
> >    ACPI tables to enumerate the mailbox. (Rob)
> >  - Described the need of using a `compatible` property.
> >  - Dropped the `alignment` property. (Krzysztof, Rafael)
> >  - Used a real address for the mailbox node. (Krzysztof)
> > 
> > Changes since v2:
> >  - Implemented the mailbox as a reserved-memory node. Add to it a
> >    `compatible` property. (Krzysztof)
> >  - Explained the relationship between the mailbox and the `enable-mehod`
> >    property of the CPU nodes.
> >  - Expanded the documentation of the binding.
> > 
> > Changes since v1:
> >  - Added more details to the description of the binding.
> >  - Added requirement a new requirement for cpu@N nodes to add an
> >    `enable-method`.
> > ---
> >  .../reserved-memory/intel,wakeup-mailbox.yaml      | 48 ++++++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml:20:111: [warning] line too long (113 > 110 characters) (line-length)


I did see this warning. I also see that none of the existing schema with
links break them into multiple lines.

Now I see that the yamllint configuration has allow-non-breakable-words: true

I will put the link in separate line.

  reply	other threads:[~2025-06-04 15:12 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-04  0:15 [PATCH v4 00/10] x86/hyperv/hv_vtl: Use a wakeup mailbox to boot secondary CPUs Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 01/10] x86/acpi: Add a helper functions to setup and access the wakeup mailbox Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 02/10] x86/acpi: Move acpi_wakeup_cpu() and helpers to smpwakeup.c Ricardo Neri
2025-06-04  9:12   ` Rafael J. Wysocki
2025-06-04 11:44     ` Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Ricardo Neri
2025-06-04  1:31   ` Rob Herring (Arm)
2025-06-04 15:17     ` Ricardo Neri [this message]
2025-06-04  9:18   ` Rafael J. Wysocki
2025-06-04 11:48     ` Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 04/10] x86/dt: Parse the " Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 05/10] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 06/10] x86/realmode: Make the location of the trampoline configurable Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 07/10] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 08/10] x86/smpwakeup: Add a helper get the address of the wakeup mailbox Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 09/10] x86/hyperv/vtl: Mark the wakeup mailbox page as private Ricardo Neri
2025-06-04  0:15 ` [PATCH v4 10/10] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs Ricardo Neri

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