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Sun, 08 Jun 2025 16:30:13 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id d75a77b69052e-4a61115000bsm48297391cf.1.2025.06.08.16.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jun 2025 16:30:12 -0700 (PDT) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Chen Wang , Inochi Amaoto , Richard Cochran , Longbin Li Cc: Han Gao , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Yixun Lan Subject: [PATCH 09/11] riscv: dts: sophgo: sg2044: Add pinctrl device Date: Mon, 9 Jun 2025 07:28:33 +0800 Message-ID: <20250608232836.784737-10-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608232836.784737-1-inochiama@gmail.com> References: <20250608232836.784737-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add pinctrl DT node and configuration for SG2044. Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index bbf4191fb87d..be20efd8e2ac 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "sg2044-cpus.dtsi" #include "sg2044-reset.h" @@ -329,6 +330,11 @@ syscon: syscon@7050000000 { clocks = <&osc>; }; + pinctrl: pinctrl@7050001000 { + compatible = "sophgo,sg2044-pinctrl"; + reg = <0x70 0x50001000 0x0 0x1000>; + }; + clk: clock-controller@7050002000 { compatible = "sophgo,sg2044-clk"; reg = <0x70 0x50002000 0x0 0x1000>; -- 2.49.0