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Sun, 08 Jun 2025 16:29:46 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id af79cd13be357-7d25a535794sm465946885a.26.2025.06.08.16.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jun 2025 16:29:45 -0700 (PDT) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Chen Wang , Inochi Amaoto , Richard Cochran , Longbin Li Cc: Han Gao , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Yixun Lan Subject: [PATCH 01/11] riscv: dts: sophgo: sg2044: Add system controller device Date: Mon, 9 Jun 2025 07:28:25 +0800 Message-ID: <20250608232836.784737-2-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608232836.784737-1-inochiama@gmail.com> References: <20250608232836.784737-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The TOP system controller device is necessary for the SG2044 clock controller. Add it to the SoC device tree. Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index d67e45f77d6e..a0c13d8d26af 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -76,6 +76,13 @@ uart3: serial@7030003000 { status = "disabled"; }; + syscon: syscon@7050000000 { + compatible = "sophgo,sg2044-top-syscon", "syscon"; + reg = <0x70 0x50000000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&osc>; + }; + rst: reset-controller@7050003000 { compatible = "sophgo,sg2044-reset", "sophgo,sg2042-reset"; -- 2.49.0