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From: Cool Lee <cool_lee@aspeedtech.com>
To: <andrew@codeconstruct.com.au>, <adrian.hunter@intel.com>,
	<ulf.hansson@linaro.org>, <joel@jms.id.au>,
	<p.zabel@pengutronix.de>, <linux-aspeed@lists.ozlabs.org>,
	<openbmc@lists.ozlabs.org>, <linux-mmc@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH 3/8] mmc: sdhci-of-aspeed: Patch HOST_CONTROL2 register missing after top reset
Date: Sun, 15 Jun 2025 11:57:58 +0800	[thread overview]
Message-ID: <20250615035803.3752235-4-cool_lee@aspeedtech.com> (raw)
In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com>

HOST_CONTROL2 register will be cleared after top reset,
it needs to be saved/resotred while reset.

Signed-off-by: Cool Lee <cool_lee@aspeedtech.com>
---
 drivers/mmc/host/sdhci-of-aspeed.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index 5e5ae1894456..10160a706334 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -336,14 +336,15 @@ static void aspeed_sdhci_reset(struct sdhci_host *host, u8 mask)
 	struct sdhci_pltfm_host *pltfm_priv;
 	struct aspeed_sdhci *aspeed_sdhci;
 	struct aspeed_sdc *aspeed_sdc;
-	u32 save_array[7];
+	u32 save_array[8];
 	u32 reg_array[] = {SDHCI_DMA_ADDRESS,
 			SDHCI_BLOCK_SIZE,
 			SDHCI_ARGUMENT,
 			SDHCI_HOST_CONTROL,
 			SDHCI_CLOCK_CONTROL,
 			SDHCI_INT_ENABLE,
-			SDHCI_SIGNAL_ENABLE};
+			SDHCI_SIGNAL_ENABLE,
+			SDHCI_AUTO_CMD_STATUS};
 	int i;
 	u16 tran_mode;
 	u32 mmc8_mode;
-- 
2.34.1


  parent reply	other threads:[~2025-06-15  3:58 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-15  3:57 [PATCH 0/8] Aspeed SDHCI driver workaround and auto tune Cool Lee
2025-06-15  3:57 ` [PATCH 1/8] mmc: sdhci-of-aspeed: Fix sdhci software reset can't be cleared issue Cool Lee
2025-06-16 13:22   ` Philipp Zabel
2025-06-18  1:34     ` Cool Lee
2025-06-18  2:14   ` Andrew Jeffery
2025-06-19  6:53     ` Cool Lee
2025-06-20  7:43       ` Andrew Jeffery
2025-06-21  8:29         ` Cool Lee
2025-06-15  3:57 ` [PATCH 2/8] mmc: sdhci-of-aspeed: Add runtime tuning Cool Lee
2025-06-18  2:31   ` Andrew Jeffery
2025-06-19  6:57     ` Cool Lee
2025-06-15  3:57 ` Cool Lee [this message]
2025-06-18  2:32   ` [PATCH 3/8] mmc: sdhci-of-aspeed: Patch HOST_CONTROL2 register missing after top reset Andrew Jeffery
2025-06-19  6:57     ` Cool Lee
2025-06-15  3:57 ` [PATCH 4/8] mmc: sdhci-of-aspeed: Get max clockk by using default api Cool Lee
2025-06-18  2:39   ` Andrew Jeffery
2025-06-20  8:18     ` Cool Lee
2025-06-15  3:58 ` [PATCH 5/8] mmc: sdhci-of-aspeed: Fix null pointer Cool Lee
2025-06-18  2:49   ` Andrew Jeffery
2025-06-20  8:18     ` Cool Lee
2025-06-15  3:58 ` [PATCH 6/8] mmc: sdhci-of-aspeed: Add output timing phase tuning Cool Lee
2025-06-18  2:51   ` Andrew Jeffery
2025-06-20  8:19     ` Cool Lee
2025-06-15  3:58 ` [PATCH 7/8] mmc: sdhci-of-aspeed: Remove timing phase Cool Lee
2025-06-18  2:56   ` Andrew Jeffery
2025-06-20 10:23     ` Cool Lee
2025-06-24 23:31       ` Andrew Jeffery
2025-06-25  0:22         ` Cool Lee
2025-06-25  0:23           ` Andrew Jeffery
2025-06-15  3:58 ` [PATCH 8/8] mmc: sdhci-of-aspeed: Add sdr50 support Cool Lee
2025-06-18  3:06   ` Andrew Jeffery

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