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Mon, 16 Jun 2025 13:52:30 -0700 (PDT) Received: from skbuf ([86.127.223.77]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adec81c60f1sm730344566b.60.2025.06.16.13.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 13:52:29 -0700 (PDT) Date: Mon, 16 Jun 2025 23:52:27 +0300 From: Vladimir Oltean To: Andrew Lunn Cc: Robert Cross , netdev@vger.kernel.org, bpf@vger.kernel.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] net: dsa: mv88e6xxx: fix external smi for mv88e6176 Message-ID: <20250616205227.2qmzv2fsbx6j533t@skbuf> References: <20250616162023.2795566-1-quantumcross@gmail.com> <3c5a8746-4d57-49d5-8a3d-5af7514c46b3@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Andrew, On Mon, Jun 16, 2025 at 08:43:14PM +0200, Andrew Lunn wrote: > On Mon, Jun 16, 2025 at 02:22:43PM -0400, Robert Cross wrote: > > According to the documents I'm looking at, the 88E6172 and > > 88E6176 both have external MDIO buses. I have brought up > > a board with two connected 88E6176 chips, each with a PHY > > that can only be managed with the MDC/MDIO_PHY pins of > > the 88E6176s. > > > > After applying this patch I was able to successfully manage > > and control these external PHYs without issue. I'm not sure > > if you have access to the 88E6176 datasheet specifically, > > but this chip absolutely does have an external MDIO. > > You are not understanding what i'm saying. This family has a single > MDIO bus controller. That controller is used by both the internal PHY > devices, plus there are two pins on the chip for external PHYs. > > All the PHYs will appear on that one MDIO bus controller. > > The MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL bit is reserved on the 6352 > family. > > Andrew Is there any addition to Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml that we could make in order to clarify which switch families have a combined internal+external MDIO bus and which ones have them separate? As you're saying, this is an area where mistakes happen relatively frequently.