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Tue, 17 Jun 2025 00:03:02 -0700 (PDT) Received: from localhost ([2001:19f0:ac00:4eb8:5400:5ff:fe30:7df3]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-23692e44fcesm6154635ad.169.2025.06.17.00.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 00:03:01 -0700 (PDT) From: Inochi Amaoto To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Alexander Sverdlin , Yixun Lan , Ze Huang , Thomas Bonnefille Cc: devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Longbin Li Subject: [PATCH v4 0/4] riscv: sophgo: cv18xx: Add reset generator support Date: Tue, 17 Jun 2025 15:01:38 +0800 Message-ID: <20250617070144.1149926-1-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Like SG2042, CV1800 Series SoCs also have simple bit reset generator. Add necessary code and bindings for it. Changes from v4: 1. patch 1: convert the compatible as entry of enum. 1. patch 2, 3: apply Alexander's tag. 1. patch 3: apply Junhui's tag. Changes from v2: 1. patch 3: fix wrong reset ID. Changes from v1: 1. rebase to v6.16-rc1 2. patch 1: apply Rob's tag 3. patch 3: fix wrong reset ID Inochi Amaoto (4): dt-bindings: reset: sophgo: Add CV1800B support reset: simple: add support for Sophgo CV1800B riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC .../bindings/reset/sophgo,sg2042-reset.yaml | 4 +- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 25 +++++ arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++ drivers/reset/reset-simple.c | 2 + 4 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h -- 2.49.0