From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A6CD287503 for ; Wed, 18 Jun 2025 11:52:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750247545; cv=none; b=TZtOIrnecez7eAVYmm0hAEJCVs/QOz5uBLdIn0cOOR+wrIq6fBhtT4T3hVfuUchb7HAjCUQ5e1puG8zS4ejv7nMTMvDAeMulCLk8oIVGDKiBBNc2g8DqQAY4OBxiAIWtrrMHuRVGWFgH6QCTDER2bj9i67xUzFEUAzL5MWliOEE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750247545; c=relaxed/simple; bh=S9pnGPpEopS2ae2vMlJNmzVk/y9G0wooLQGCC/s9bSw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=IsSCwsXBXyb+XDqaIR5MdPtgkDGtJCyW9Pry7Zwz8O4ZdILQBhym4cwzYalkGZPNx/MG0d9cBN4Uh7Vp05Pml34cZway2ZxpPR5RcKDqwUqDZOgsolZE58SNP9TOWYDLqKw5U3UBMQwzi2R8mZnezw8D1ZQ1SEPVwfE8H8zphtk= ARC-Authentication-Results:i=1; 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charset="utf-8" X-RootMTR: 20250618115220eucas1p2b9d37e8cdd1997fa010f51cecdea5e4f X-EPHeader: CA X-CMS-RootMailID: 20250618115220eucas1p2b9d37e8cdd1997fa010f51cecdea5e4f References: <20250616163831.8138-3-linux.amoon@gmail.com> Hello :) > +#define INTSTAT_FALL2 BIT(24) > +#define INTSTAT_FALL1 BIT(20) > +#define INTSTAT_FALL0 BIT(16) > +#define INTSTAT_RISE2 BIT(8) > +#define INTSTAT_RISE1 BIT(4) > +#define INTSTAT_RISE0 BIT(0) > + > +#define INTCLEAR_FALL2 BIT(24) > +#define INTCLEAR_FALL1 BIT(20) > +#define INTCLEAR_FALL0 BIT(16) > +#define INTCLEAR_RISE2 BIT(8) > +#define INTCLEAR_RISE1 BIT(4) > +#define INTCLEAR_RISE0 BIT(0) > + /* Map INTSTAT bits to INTCLEAR bits */ > + if (val_irq & INTSTAT_FALL2) > + clearirq |= INTCLEAR_FALL2; > + else if (val_irq & INTSTAT_FALL1) > + clearirq |= INTCLEAR_FALL1; > + else if (val_irq & INTSTAT_FALL0) > + clearirq |= INTCLEAR_FALL0; > + else if (val_irq & INTSTAT_RISE2) > + clearirq |= INTCLEAR_RISE2; > + else if (val_irq & INTSTAT_RISE1) > + clearirq |= INTCLEAR_RISE1; > + else if (val_irq & INTSTAT_RISE0) > + clearirq |= INTCLEAR_RISE0; This implies that only these 6 bits are used. Is this true for all SoCs supported by this driver? My understanding is that Exynos 5433 in particular uses bits 7:0 for rise interrupts and 23:16 for fall interrupts. When I tested this patch (both alone and the whole series) on 5433 by running some CPU load, the interrupt seemed to not fire consistently: /sys/class/thermal/cooling_device1/cur_state would never go above 1 (which is consistent with the interrupt firing once, not getting cleared and never firing again; without this patch, it consistently went up to 6) and I got a quick reboot every time. Thank you, Mateusz Majewski