From: Mihai Sain <mihai.sain@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<claudiu.beznea@tuxon.dev>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Mihai Sain <mihai.sain@microchip.com>
Subject: [PATCH v3 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs
Date: Thu, 19 Jun 2025 10:06:34 +0300 [thread overview]
Message-ID: <20250619070636.8844-1-mihai.sain@microchip.com> (raw)
This patch series adds cache configuration for Microchip SAMA7D and SAMA7G MPUs.
The cache configuration is described in datasheet chapter 15.2.
Changelog:
v2 -> v3:
- Remove the l1-cache node
- Move the L1 cache properties in the cpu node
- Align with device node requirements for cpu:
https://devicetree-specification.readthedocs.io/en/latest/chapter3-devicenodes.html#internal-l1-cache-properties
v1 -> v2:
- Remove the cache-unified property from l1-cache node
Mihai Sain (2):
ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
arch/arm/boot/dts/microchip/sama7d65.dtsi | 10 ++++++++++
arch/arm/boot/dts/microchip/sama7g5.dtsi | 10 ++++++++++
2 files changed, 20 insertions(+)
base-commit: fb4d33ab452ea254e2c319bac5703d1b56d895bf
--
2.50.0
next reply other threads:[~2025-06-19 7:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 7:06 Mihai Sain [this message]
2025-06-19 7:06 ` [PATCH v3 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Mihai Sain
2025-06-19 7:06 ` [PATCH v3 2/2] ARM: dts: microchip: sama7g5: " Mihai Sain
2025-07-10 7:34 ` [PATCH v3 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Claudiu Beznea
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