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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4535e9844a9sm86192885e9.12.2025.06.21.04.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Jun 2025 04:21:00 -0700 (PDT) Date: Sat, 21 Jun 2025 12:20:59 +0100 From: David Laight To: Huacai Chen Cc: Bibo Mao , Tianrui Zhao , Xianglai Li , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 9/9] LoongArch: KVM: INTC: Add address alignment check Message-ID: <20250621122059.6caf299a@pumpkin> In-Reply-To: References: <20250611014651.3042734-1-maobibo@loongson.cn> <20250611015145.3042884-1-maobibo@loongson.cn> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, 19 Jun 2025 16:47:22 +0800 Huacai Chen wrote: > Hi, Bibo, >=20 > On Wed, Jun 11, 2025 at 9:51=E2=80=AFAM Bibo Mao wr= ote: > > > > IOCSR instruction supports 1/2/4/8 bytes access, the address should > > be naturally aligned with its access size. Here address alignment > > check is added in eiointc kernel emulation. > > > > At the same time len must be 1/2/4/8 bytes from iocsr exit emulation > > function kvm_emu_iocsr(), remove the default case in switch case > > statements. =20 > Robust code doesn't depend its callers do things right, so I suggest > keeping the default case, which means we just add the alignment check > here. kernel code generally relies on callers to DTRT - except for values that come from userspace. Otherwise you get unreadable and slow code that continuously checks for things that can't happen. David >=20 > And I think this patch should also Cc stable and add a Fixes tag. >=20 >=20 > Huacai >=20 > > > > Signed-off-by: Bibo Mao > > --- > > arch/loongarch/kvm/intc/eiointc.c | 21 +++++++++++++-------- > > 1 file changed, 13 insertions(+), 8 deletions(-) > > > > diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/int= c/eiointc.c > > index 8b0d9376eb54..4e9d12300cc4 100644 > > --- a/arch/loongarch/kvm/intc/eiointc.c > > +++ b/arch/loongarch/kvm/intc/eiointc.c > > @@ -311,6 +311,12 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, > > return -EINVAL; > > } > > > > + /* len must be 1/2/4/8 from function kvm_emu_iocsr() */ > > + if (addr & (len - 1)) { > > + kvm_err("%s: eiointc not aligned addr %llx len %d\n", _= _func__, addr, len); > > + return -EINVAL; > > + } > > + > > vcpu->stat.eiointc_read_exits++; > > spin_lock_irqsave(&eiointc->lock, flags); > > switch (len) { > > @@ -323,12 +329,9 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, > > case 4: > > ret =3D loongarch_eiointc_readl(vcpu, eiointc, addr, va= l); > > break; > > - case 8: > > + default: > > ret =3D loongarch_eiointc_readq(vcpu, eiointc, addr, va= l); > > break; > > - default: > > - WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx,= size %d\n", > > - __func__, addr, len); > > } > > spin_unlock_irqrestore(&eiointc->lock, flags); > > > > @@ -682,6 +685,11 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, > > return -EINVAL; > > } > > > > + if (addr & (len - 1)) { > > + kvm_err("%s: eiointc not aligned addr %llx len %d\n", _= _func__, addr, len); > > + return -EINVAL; > > + } > > + > > vcpu->stat.eiointc_write_exits++; > > spin_lock_irqsave(&eiointc->lock, flags); > > switch (len) { > > @@ -694,12 +702,9 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, > > case 4: > > ret =3D loongarch_eiointc_writel(vcpu, eiointc, addr, v= al); > > break; > > - case 8: > > + default: > > ret =3D loongarch_eiointc_writeq(vcpu, eiointc, addr, v= al); > > break; > > - default: > > - WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx,= size %d\n", > > - __func__, addr, len); > > } > > spin_unlock_irqrestore(&eiointc->lock, flags); > > > > -- > > 2.39.3 > > =20 >=20