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Mon, 23 Jun 2025 21:09:26 -0700 (PDT) Received: from google.com ([2401:fa00:1:10:9e4d:2f37:d5ea:8954]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-749b5e4069csm679035b3a.65.2025.06.23.21.09.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 21:09:26 -0700 (PDT) Date: Tue, 24 Jun 2025 12:09:22 +0800 From: Chen-Yu Tsai To: AngeloGioacchino Del Regno Cc: linux-mediatek@lists.infradead.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, weiyi.lu@mediatek.com, tinghan.shen@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: Re: [PATCH v1 1/2] arm64: dts: mediatek: mt8195: Add subsys clks for PCIe power domains Message-ID: <20250624040922.GA1077353@google.com> References: <20250402090615.25871-1-angelogioacchino.delregno@collabora.com> <20250402090615.25871-2-angelogioacchino.delregno@collabora.com> <33847b76-11b5-4233-a5e6-9f8fd3c691a2@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <33847b76-11b5-4233-a5e6-9f8fd3c691a2@collabora.com> On Wed, Apr 02, 2025 at 12:07:16PM +0200, AngeloGioacchino Del Regno wrote: > Il 02/04/25 11:34, Chen-Yu Tsai ha scritto: > > On Wed, Apr 2, 2025 at 5:10 PM AngeloGioacchino Del Regno > > wrote: > > > > > > The PCIe MAC needs the sram to be powered on for internal IP > > > access and it has always worked before because the bootloader > > > on Chromebooks was leaving the PCIe PERI_AO MEM clocks on > > > before booting the kernel. > > > Add the SRAM (mem) clock as a subsystem clock on the PCIe MAC > > > P0 and P1 to correctly describe the hardware and to avoid any > > > issue with bootloaders behaving differently. > > > > > > Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller") > > > Signed-off-by: AngeloGioacchino Del Regno > > > --- > > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > > index b33726da900b..0cb96cba727a 100644 > > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > > @@ -792,12 +792,16 @@ power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { > > > > > > power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { > > > reg = ; > > > + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; > > > + clock-names = "ss-pextp0-mem"; > > > > Doesn't the PCIe host controller already reference this clock? > > > > > mediatek,infracfg = <&infracfg_ao>; > > > #power-domain-cells = <0>; > > > }; > > > > > > power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { > > > reg = ; > > > + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P1_MEM>; > > > + clock-names = "ss-pextp1-mem"; > > > > Not this one though, since: > > > > /* Designer has connect pcie1 with peri_mem_p0 clock */ > > <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; > > > > I'm not sure what this comment refers to - as in, whether this is referring > to the board designer or to the SoC//IP designer... When MediaTek says "designer" they are referring to the hardware designer, in this case I believe it would be the SoC-level hardware designer / integrator. > ...but if MediaTek can clarify, I'd be happy :-) > > Cheers, > Angelo > > > > > ChenYu > > > > > mediatek,infracfg = <&infracfg_ao>; > > > #power-domain-cells = <0>; > > > }; > > > -- > > > 2.48.1 > > > > > > >