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Tue, 24 Jun 2025 01:15:12 -0700 (PDT) Received: from localhost.localdomain ([41.79.198.24]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6e810977esm1261465f8f.83.2025.06.24.01.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 01:15:12 -0700 (PDT) From: Khalid Ali X-Google-Original-From: Khalid Ali X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516091534.3414310-1-kirill.shutemov@linux.intel.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit >Both Intel and AMD CPUs support 5-level paging, which is expected to >become more widely adopted in the future. > >Remove CONFIG_X86_5LEVEL. > >In preparation to that remove CONFIG_DYNAMIC_MEMORY_LAYOUT and make >SPARSEMEM_VMEMMAP the only memory model. > >v2: > - Fix 32-bit build by wrapping p4d_set_huge() and p4d_clear_huge() in > #if CONFIG_PGTABLE_LEVELS > 4; > - Rebased onto current tip/master; > >Kirill A. Shutemov (3): > x86/64/mm: Always use dynamic memory layout > x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model > x86/64/mm: Make 5-level paging support unconditional > > Documentation/arch/x86/cpuinfo.rst | 8 ++--- > .../arch/x86/x86_64/5level-paging.rst | 9 ------ > arch/x86/Kconfig | 32 ++----------------- > arch/x86/Kconfig.cpufeatures | 4 --- > arch/x86/boot/compressed/pgtable_64.c | 11 ++----- > arch/x86/boot/header.S | 4 --- > arch/x86/boot/startup/map_kernel.c | 5 +-- > arch/x86/include/asm/page_64.h | 2 -- > arch/x86/include/asm/page_64_types.h | 11 ------- > arch/x86/include/asm/pgtable_64_types.h | 24 -------------- > arch/x86/kernel/alternative.c | 2 +- > arch/x86/kernel/head64.c | 4 --- > arch/x86/kernel/head_64.S | 2 -- > arch/x86/mm/init.c | 4 --- > arch/x86/mm/init_64.c | 9 +----- > arch/x86/mm/pgtable.c | 2 +- > drivers/firmware/efi/libstub/x86-5lvl.c | 2 +- > scripts/gdb/linux/pgtable.py | 4 +-- > 18 files changed, 13 insertions(+), 126 deletions(-) I think i am too late, however this is completely wrong. There are still processors that doesn't support 5-level paging which is mordern. We may call those processors old, however they are still common and used. So this patch seem too early for that. Some intel core-i5 and core-i7 doesn't support 5-level paging at all. This will break x86_64 cpus that doesn't support 5-level paging.