From: yankei.fong@altera.com
To: dinguyen@kernel.org
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
krzk+dt@kernel.org, linux-kernel@vger.kernel.org,
matthew.gerlach@altera.com, robh@kernel.org,
yankei.fong@altera.com
Subject: [PATCH 0/4] Add 4-bit SPI bus width on target devices
Date: Mon, 30 Jun 2025 10:44:44 +0800 [thread overview]
Message-ID: <20250630024444.3071-1-yankei.fong@altera.com> (raw)
In-Reply-To: <70e3a367-8d9d-477b-9858-9f2a7b97bbca@kernel.org>
From: Fong, Yan Kei <yan.kei.fong@altera.com>
The changes required for the QSPI subsystem. With this implementation, the
read performance will be greater compare to single bus width when trying
to read the QSPI flash chips. Below is the test results:
$cat /sys/kernel/debug/spi-nor/spi0.0/params
...
...
opcodes
read 0x6c -> from micron QSPI spec, 6c indicates quad output fast read
...
...
protocols
read 1S-1S-4S
next prev parent reply other threads:[~2025-06-30 2:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 6:52 yankei.fong
2025-06-24 6:52 ` [PATCH 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width yankei.fong
2025-08-31 1:40 ` Dinh Nguyen
2025-06-24 6:52 ` [PATCH 2/4] arm64: dts: socfpga: stratix10: " yankei.fong
2025-06-24 6:52 ` [PATCH 3/4] arm64: dts: socfpga: agilex: " yankei.fong
2025-06-24 6:52 ` [PATCH 4/4] arm64: dts: socfpga: agilex5: " yankei.fong
2025-06-24 17:32 ` [PATCH 0/4] Add 4-bit SPI bus width on target devices Dinh Nguyen
2025-06-30 2:44 ` yankei.fong [this message]
2025-07-09 7:00 ` Fong, Yan Kei
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