From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5EF51DED64 for ; Mon, 30 Jun 2025 08:08:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751270921; cv=none; b=pKjjvoanDO6vC5BPum/zbfebfk0NVWQUZzrL+9hW8ZV1FSsSU/70JTARQ2UxKYKvvXcHmK6wHgJd6wnKe3xiWri/LQZVCfqAuw24Rba1gNhaXS9zq5bLBNXjLsvRE2ozBAWLSmo45s0+jmWL2L/2pwKWspEhq+0h3MDIPZU4WNs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751270921; c=relaxed/simple; bh=LrKcaVKYdh9u/OMq6Y0X9Dgx6h4vHgCQJ9ijtS8M2pE=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=deDID6Paqe7beuJk/CwN33tbKj8sZsu3TuDofKAQg3eD/+tdkrxSz67fv9VbAQMPZmYiYm0SjcmcGXDUiIk1voQHtXKTcsxDG9SC8k/BKMGb4BlB3+gUBEpOxQzoCR5yMGVA42JkXhldNJoQybCzR8B24Xy220v5TYVi4oz7qR0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Tp51RyP2; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Tp51RyP2" X-UUID: 67b1143e558911f0b1510d84776b8c0b-20250630 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=hA5xu5/nGaa0Kk0uJvXqrtZyhBddrOKROYtY/NQCRsk=; b=Tp51RyP2i6WJs8h6+tA04Owau4vBZ3qbghhida59sdfW2YwykI7+sbpToOVUpE7Ql8AlyS6yDQ59yZ+wciC5SOdUcLhlx259wr3h40LHGa4IjhlCJl1VN+PcQ3Y4ZGZi/KcJjAhz3Vq6Vp7SiczMoEyJ5vtTzn4HuYxhHV2eD+s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:541e71b3-6725-4c82-a032-3b52671bce12,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:9eb4ff7,CLOUDID:229bc75f-2aa0-4c76-8faa-804d844c7164,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:-3,IP:ni l,URL:99|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0, LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULS,TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 67b1143e558911f0b1510d84776b8c0b-20250630 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 304016550; Mon, 30 Jun 2025 16:08:28 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 30 Jun 2025 16:08:26 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 30 Jun 2025 16:08:26 +0800 From: Liankun Yang To: , , , , , , , , , CC: , , , Subject: [PATCH v5 1/1] drm/mediatek: Adjust bandwidth limit for DP Date: Mon, 30 Jun 2025 15:58:06 +0800 Message-ID: <20250630080824.7107-1-liankun.yang@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N By adjusting the order of link training and relocating it to HPD, link training can identify the usability of each lane in the current link. It also supports handling signal instability and weakness due to environmental issues, enabling the acquisition of a stable bandwidth for the current link. Subsequently, DP work can proceed based on the actual maximum bandwidth. It should training in the hpd event thread. Check the mode with lane count and link rate of training. If we're eDP and capabilities were already parsed we can skip reading again because eDP panels aren't hotpluggable hence the caps and training information won't ever change in a boot life Therefore, bridge typec judgment is required for edp training in atomic_enable function. Because DP will enter idle pattern state after DP training,the current DP link state is ready and can be prepared to output the video. Therefore, the following actions do not require the wall-mounted aux_panel power, and set DP enable to true. Signed-off-by: Liankun Yang --- Change in V5: - Fixed the issue that the 4th version of the patch caused DP to have no screen. Per suggestion from the previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20250625095446.31726-1-liankun.yang@mediatek.com/ Change in V4: - Tested the internal eDP display on MT8195 Tomato and it is fine. Per suggestion from the previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20250318140236.13650-2-liankun.yang@mediatek.com/ Change in V3: - Remove 'mtk_dp->enabled = false" in atomic disable. - Remove 'mtk_dp->enabled = true" in atomic enable. Per suggestion from the previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20241025083036.8829-4-liankun.yang@mediatek.com/ Change in V2: - Adjust DP training timing. - Adjust parse capabilities timing. - Add power on/off for connect/disconnect. Per suggestion from the previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240315015233.2023-1-liankun.yang@mediatek.com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 45 ++++++++++++++++++------------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index a5b10b2545dc..1010263f2510 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1976,6 +1976,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev) struct mtk_dp *mtk_dp = dev; unsigned long flags; u32 status; + int ret; if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in) msleep(100); @@ -1994,9 +1995,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev) memset(&mtk_dp->info.audio_cur_cfg, 0, sizeof(mtk_dp->info.audio_cur_cfg)); + mtk_dp->enabled = false; + /* power off aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + mtk_dp->need_debounce = false; mod_timer(&mtk_dp->debounce_timer, jiffies + msecs_to_jiffies(100) - 1); + } else { + mtk_dp_aux_panel_poweron(mtk_dp, true); + + ret = mtk_dp_parse_capabilities(mtk_dp); + if (ret) + drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); + + /* Training */ + ret = mtk_dp_training(mtk_dp); + if (ret) + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); + + mtk_dp->enabled = true; } } @@ -2161,17 +2181,6 @@ static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge, } drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc); - - /* - * Parse capability here to let atomic_get_input_bus_fmts and - * mode_valid use the capability to calculate sink bitrates. - */ - if (mtk_dp_parse_capabilities(mtk_dp)) { - drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); - drm_edid_free(drm_edid); - drm_edid = NULL; - } - if (drm_edid) { /* * FIXME: get rid of drm_edid_raw() @@ -2366,11 +2375,13 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, mtk_dp_aux_panel_poweron(mtk_dp, true); - /* Training */ - ret = mtk_dp_training(mtk_dp); - if (ret) { - drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); - goto power_off_aux; + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) { + /* Training */ + ret = mtk_dp_training(mtk_dp); + if (ret) { + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); + goto power_off_aux; + } } ret = mtk_dp_video_config(mtk_dp); @@ -2390,7 +2401,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, sizeof(mtk_dp->info.audio_cur_cfg)); } - mtk_dp->enabled = true; mtk_dp_update_plugged_status(mtk_dp); return; @@ -2405,7 +2415,6 @@ static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge, { struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); - mtk_dp->enabled = false; mtk_dp_update_plugged_status(mtk_dp); mtk_dp_video_enable(mtk_dp, false); mtk_dp_audio_mute(mtk_dp, true); -- 2.45.2