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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?Q?C3YIfcG4ydvW0b9FaAD2wkr0s+QkKt0n//5kP9ym9VnCnNpInyQusnOfX0?= =?iso-8859-1?Q?MUL2vPD4v40xzJl/A1gliw137pMwtgUV0AgRJ8wryxB2z8fMTB/A6i/OKY?= =?iso-8859-1?Q?6DeRKKmVMzMt1UMC+9reICyqjn+5SqnB1ndNFmYlLROAqV9Exn2ZAAHzx1?= =?iso-8859-1?Q?mEF+Awza8EdZCXY7Gxglu/EfW9PcZt/h4lhLPNRnU4R9bUAlAJSB43QMQC?= =?iso-8859-1?Q?BZxiKB6xzHjxkhoS3L80zVzYnEoOBZP+AlGZcfK6iSqk1ZUICtNyRFuffI?= =?iso-8859-1?Q?gJkopqLJ1Q7uRuyB08Q4t9Qzwlh3w7IaXx1uXUNahud5ncYN4ReN2kjMDw?= =?iso-8859-1?Q?cIzoOElDl3THZVLLf7c4MHHjSg5Vhr2bDAfui7kgiq66dDub7jcHoze7Up?= =?iso-8859-1?Q?ASDlbvJDZu63DqI4vv/5jZhrt/65aX3aGrozF8MuzDL2PmSffbFSIrqK/y?= =?iso-8859-1?Q?FKmBDHOwj7FTA+y5p+pFE0vh77MGTEt8Y0Hoo+DuoDqwUiWbzEM9syGfMp?= =?iso-8859-1?Q?8vXOSuWYcCX9WR8HqLSLdyf69fs/RYqHbzqIcoZkZgvzHpn5FU8v93VGXc?= =?iso-8859-1?Q?mLx5f8OJXzTM3s/yJAZkMMFUDtu++gFlNtfbSk/6R/aVO2Gx54anH5E1cq?= =?iso-8859-1?Q?9gu4mtVwj77vxRRpEwqLEHsvDJSUt34xdaqG27kCzpV611yKkkxATUNBn3?= =?iso-8859-1?Q?sQM1vCsVL/1Pkhq0gO3MXN449W51UhKe7DoNKT3p5DzdULAqXyL4euwWl3?= =?iso-8859-1?Q?zAC8rjU8PHTLFtEjtbjdi6UfOCA0/V+j/HUWctk0ZET3+IEhyvVRI3hUhG?= =?iso-8859-1?Q?Ri6P5u0qt3wKqDep6n7UW1wUlW2pkQAWhT8K/mbYYx749YiGXb7YYn9PdU?= =?iso-8859-1?Q?SilwSxp1IOJmb9XBcVtOJUAOdfN9kWPFY2i0Li+QEjGqXKfxObDQdKDl/I?= =?iso-8859-1?Q?Mmi4oxiR2vqLgeCmLrer/veMYa96EvIxajhAYqQDkfH2FtkqKG+03N9DZr?= =?iso-8859-1?Q?GY4h68wWpqumyLQtjgRr4olEaJkiim/LIJumzguiwXQvRdY6Q0nblODM3X?= =?iso-8859-1?Q?FhlphQQP4XX5vZgR7AFuhR26FMZWYuUsFD+K6ywVj6wH7mrCP2C8jP84bT?= =?iso-8859-1?Q?BdV8Xq/+KdV/NBTdETyw4Z706ngAcgqWy71qi2e6wRk0vBCvmQMPGd7D0l?= =?iso-8859-1?Q?dZWyEEw4pNAvA8EFzw7XlkRXwMXsKpSCPKbD5nQNG20sFnOtoyP3K2lvFd?= =?iso-8859-1?Q?5+hYxZYsSgYkGHQBu4JxWgvoGKAZqqrfe+P1GD2J+KPV11Q37eVXOVWbYK?= =?iso-8859-1?Q?utsiY8CDW+eTluOoUwsF8Ml3tQSqMn5iYUugkVSfQdPw+NPINeNsx+Rh9U?= =?iso-8859-1?Q?86uIcG2cQknf2AFZx+p9IsdobCu3JKBaKgS5ffTNCD79CPcREzIFlFf3s5?= =?iso-8859-1?Q?pWIi/mtHVZLyjN4yUCOS5M/qfQB6mDIL6bnzzBtKkft79wRXWjdl+lTlrv?= =?iso-8859-1?Q?7HP71KFdNXhXXF7+vfs0LG8fg8rZOraCsUwZgXD/agqILduUfHxKEQH173?= =?iso-8859-1?Q?4IB0QC02JibmVOoAtWSjAToPTHA5zTwn3+xoQPQ2mcqorTvCkEOavFjKwK?= =?iso-8859-1?Q?11Odjmqcvl4jhvslQcv7yIfAt/y6YZs4bU?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 31467194-76a8-42e9-6fb1-08ddb7d5acc9 X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 12:57:31.3763 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VTOBNbL3SRJuBEg7V50snBULqHlt6MzKdxRDAw992TrxxsTdbm156Ah3eyaA9dgK5D48hgMMKl5ZBzrsEK5BUg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8206 On Fri, Jun 27, 2025 at 02:14:40PM +0300, Nikolay Borisov wrote: > > > On 6/25/25 19:52, Nikolay Borisov wrote: > > > > > > On 6/24/25 17:16, Yazen Ghannam wrote: > > > The threshold_bank structure is a container for one or more > > > threshold_block structures. Currently, the container has a single > > > pointer to the 'first' threshold_block structure which then has a linked > > > list of the remaining threshold_block structures. > > > > > > This results in an extra level of indirection where the 'first' block is > > > checked before iterating over the remaining blocks. > > > > > > Remove the indirection by including the head of the block list in the > > > threshold_bank structure which already acts as a container for all the > > > bank's thresholding blocks. > > > > > > Reviewed-by: Qiuxu Zhuo > > > Tested-by: Tony Luck > > > Reviewed-by: Tony Luck > > > Signed-off-by: Yazen Ghannam > > > --- > > > > > > Notes: > > >      Link: > > >      https://lore.kernel.org/r/20250415-wip-mca-updates- > > > v3-4-8ffd9eb4aa56@amd.com > > >      v3->v4: > > >      * No change. > > >      v2->v3: > > >      * Added tags from Qiuxu and Tony. > > >      v1->v2: > > >      * New in v2. > > > > > >   arch/x86/kernel/cpu/mce/amd.c | 43 +++++++++++ > > > +------------------------------- > > >   1 file changed, 12 insertions(+), 31 deletions(-) > > > > > > diff --git a/arch/x86/kernel/cpu/mce/amd.c > > > b/arch/x86/kernel/cpu/mce/ amd.c > > > index 0ffbee329a8c..5d351ec863cd 100644 > > > --- a/arch/x86/kernel/cpu/mce/amd.c > > > +++ b/arch/x86/kernel/cpu/mce/amd.c > > > @@ -241,7 +241,8 @@ struct threshold_block { > > >   struct threshold_bank { > > >       struct kobject        *kobj; > > > -    struct threshold_block    *blocks; > > > +    /* List of threshold blocks within this MCA bank. */ > > > +    struct list_head    miscj; > > >   }; > > >   static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); > > > @@ -900,9 +901,9 @@ static void log_and_reset_block(struct > > > threshold_block *block) > > >    */ > > >   static void amd_threshold_interrupt(void) > > >   { > > > -    struct threshold_block *first_block = NULL, *block = NULL, *tmp > > > = NULL; > > > -    struct threshold_bank **bp = this_cpu_read(threshold_banks); > > > +    struct threshold_bank **bp = this_cpu_read(threshold_banks), > > > *thr_bank; > > >       unsigned int bank, cpu = smp_processor_id(); > > > +    struct threshold_block *block, *tmp; > > >       /* > > >        * Validate that the threshold bank has been initialized > > > already. The > > > @@ -916,16 +917,11 @@ static void amd_threshold_interrupt(void) > > >           if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) > > >               continue; > > > > > > > > nit: I wonder if instead of using per_cpu and manual bit testing can't a > > direct > > call to x86_this_cpu_test_bit be a better solution. The assembly looks > > like: > > > > [OLD] > > > > xorl    %r14d, %r14d    # ivtmp.245 > > movq    %rax, 8(%rsp)   # cpu, %sfp > > # arch/x86/kernel/cpu/mce/amd.c:917:        if (!(per_cpu(bank_map, cpu) > > & BIT_ULL(bank))) > > movq    $bank_map, %rax #, __ptr > > movq    %rax, (%rsp)    # __ptr, %sfp > > .L236: > > movq    8(%rsp), %rax   # %sfp, cpu > > # arch/x86/kernel/cpu/mce/amd.c:917:        if (!(per_cpu(bank_map, cpu) > > & BIT_ULL(bank))) > > movq    (%rsp), %rsi    # %sfp, __ptr > > # arch/x86/kernel/cpu/mce/amd.c:917:        if (!(per_cpu(bank_map, cpu) > > & BIT_ULL(bank))) > > movq    __per_cpu_offset(,%rax,8), %rax # __per_cpu_offset[cpu_23], > > __per_cpu_offset[cpu_23] > > # arch/x86/kernel/cpu/mce/amd.c:917:        if (!(per_cpu(bank_map, cpu) > > & BIT_ULL(bank))) > > movq    (%rax,%rsi), %rax > > # arch/x86/kernel/cpu/mce/amd.c:917:        if (!(per_cpu(bank_map, cpu) > > & BIT_ULL(bank))) > > btq %r14, %rax > > > > [NEW] > > > > xorl    %r15d, %r15d    # ivtmp.246 > > .L236: > > # 917 "arch/x86/kernel/cpu/mce/amd.c" 1 > > btl %r15d, %gs:bank_map(%rip)   # ivtmp.246, *_9 > > > > > > That way you end up with a single btl (but I guess a version that uses > > btq should be added as well) > > inside the loop rather than a bunch of instructions moving data around > > for per_cpu. > > > > Alternatively, since this is running in interrupt context can't you use > > directly this_cpu_read(bank_map) and eliminate the smp_processor_id > > invocation? > > > Actually the total number of banks are at most 128 as per the layout of > MCG_CAP register, so using btl is fine. Also I'm not sure why the original > code uses BIT_ULL vs just BIT since we can't have a 64bit value. > > Hi Nikolay, MCG_CAP[Count] is an 8-bit field, so we can (potentially) have up to 255 MCA banks. "bank_map" is a bitmask, and current systems can have up to 64 MCA banks. That is why BIT_ULL is needed. Thanks, Yazen