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From: Borislav Petkov <bp@alien8.de>
To: Vijay Balakrishna <vijayb@linux.microsoft.com>
Cc: Tony Luck <tony.luck@intel.com>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	James Morse <james.morse@arm.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Robert Richter <rric@kernel.org>,
	linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	Tyler Hicks <code@tyhicks.com>, Marc Zyngier <maz@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	devicetree@vger.kernel.org
Subject: Re: [v11 PATCH 1/2] EDAC: Add EDAC driver for ARM Cortex A72 cores
Date: Mon, 30 Jun 2025 18:33:57 +0200	[thread overview]
Message-ID: <20250630163357.GGaGK8dbT4fp68PplM@fat_crate.local> (raw)
In-Reply-To: <1748487628-30123-2-git-send-email-vijayb@linux.microsoft.com>

On Wed, May 28, 2025 at 08:00:27PM -0700, Vijay Balakrishna wrote:
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index a8f2d8f6c894..136416f43b44 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -88,3 +88,4 @@ obj-$(CONFIG_EDAC_NPCM)			+= npcm_edac.o
>  obj-$(CONFIG_EDAC_ZYNQMP)		+= zynqmp_edac.o
>  obj-$(CONFIG_EDAC_VERSAL)		+= versal_edac.o
>  obj-$(CONFIG_EDAC_LOONGSON)		+= loongson_edac.o
> +obj-$(CONFIG_EDAC_CORTEX_A72)		+= edac_a72.o

The drivers filename format is

	edac_<something>.c

So a72_edac.c

> diff --git a/drivers/edac/edac_a72.c b/drivers/edac/edac_a72.c
> new file mode 100644
> index 000000000000..4f40616d40a0
> --- /dev/null
> +++ b/drivers/edac/edac_a72.c
> @@ -0,0 +1,230 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Cortex A72 EDAC L1 and L2 cache error detection
> + *
> + * Copyright (c) 2020 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + * Copyright (c) 2025 Microsoft Corporation, <vijayb@linux.microsoft.com>
> + *
> + * Based on Code from:
> + * Copyright (c) 2018, NXP Semiconductor
> + * Author: York Sun <york.sun@nxp.com>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/bitfield.h>
> +#include <asm/smp_plat.h>
> +
> +#include "edac_module.h"
> +
> +#define DRVNAME		"edac-a72"
> +
> +#define SYS_CPUMERRSR_EL1	sys_reg(3, 1, 15, 2, 2)
> +#define SYS_L2MERRSR_EL1	sys_reg(3, 1, 15, 2, 3)
> +
> +#define CPUMERRSR_EL1_RAMID		GENMASK(30, 24)
> +#define L2MERRSR_EL1_CPUID_WAY	GENMASK(21, 18)
> +
> +#define CPUMERRSR_EL1_VALID		BIT(31)
> +#define CPUMERRSR_EL1_FATAL		BIT(63)
> +#define L2MERRSR_EL1_VALID		BIT(31)
> +#define L2MERRSR_EL1_FATAL		BIT(63)
> +
> +#define L1_I_TAG_RAM	0x00
> +#define L1_I_DATA_RAM	0x01
> +#define L1_D_TAG_RAM	0x08
> +#define L1_D_DATA_RAM	0x09
> +#define TLB_RAM			0x18
> +
> +#define MESSAGE_SIZE	64

I had written

"Please group all defines together, align them vertically and then put other
definitions below. Look at other drivers for inspiration."

in my previous review

Message-ID: <20250519085130.GFaCrxEnZvaoETKrao@fat_crate.local>

but seems like this got ignored.

Oh well, I'll ignore your submission too until you address *all* my review
feedback.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

  reply	other threads:[~2025-06-30 16:34 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-29  3:00 [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Vijay Balakrishna
2025-05-29  3:00 ` [v11 PATCH 1/2] EDAC: Add EDAC driver for ARM Cortex A72 cores Vijay Balakrishna
2025-06-30 16:33   ` Borislav Petkov [this message]
2025-05-29  3:00 ` [v11 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-05-29  9:55 ` [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Borislav Petkov
2025-06-27 16:49   ` Vijay Balakrishna

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