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Sun, 06 Jul 2025 20:53:54 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 0/2] Few timer and AIA fixes for KVM RISC-V Date: Mon, 7 Jul 2025 09:23:42 +0530 Message-ID: <20250707035345.17494-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RISC-V Privileged specificaiton says the following: "WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level." Based on the above, if there is pending VS-timer interrupt when the host (aka HS-mode) executes WFI then such a WFI will simply become NOP and not do anything. This result in QEMU RISC-V consuming a lot of CPU time on the x86 machine where it is running. The PATCH1 solves this issue by adding appropriate cleanup in KVM RISC-V timer virtualization. As a result PATCH1, race conditions in updating HGEI[E|P] CSRs when a VCPU is moved from one host CPU to another are being observed on QEMU so the PATCH2 tries to minimize the chances of these race conditions. Changes since v1: - Added more details about race condition in PATCH2 commit description. Anup Patel (2): RISC-V: KVM: Disable vstimecmp before exiting to user-space RISC-V: KVM: Move HGEI[E|P] CSR access to IMSIC virtualization arch/riscv/include/asm/kvm_aia.h | 4 ++- arch/riscv/kvm/aia.c | 51 +++++--------------------------- arch/riscv/kvm/aia_imsic.c | 45 ++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu.c | 2 -- arch/riscv/kvm/vcpu_timer.c | 16 ++++++++++ 5 files changed, 71 insertions(+), 47 deletions(-) -- 2.43.0