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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4D.mail.protection.outlook.com (10.167.242.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.20 via Frontend Transport; Wed, 9 Jul 2025 03:37:45 +0000 Received: from BLR-L-NUPADHYA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Jul 2025 22:37:31 -0500 From: Neeraj Upadhyay To: CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v8 15/35] x86/apic: Unionize apic regs for 32bit/64bit access w/o type casting Date: Wed, 9 Jul 2025 09:02:22 +0530 Message-ID: <20250709033242.267892-16-Neeraj.Upadhyay@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709033242.267892-1-Neeraj.Upadhyay@amd.com> References: <20250709033242.267892-1-Neeraj.Upadhyay@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4D:EE_|SA3PR12MB9198:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e60b438-eb19-4b29-5f09-08ddbe99f7c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|7416014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 03:37:45.2219 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e60b438-eb19-4b29-5f09-08ddbe99f7c5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9198 Define apic_page construct to unionize APIC register 32bit/64bit accesses and use it in apic_{get|set}*() to avoid using type casting. As Secure AVIC APIC driver requires accessing APIC page at byte offsets (to get an APIC register's bitmap start address), support byte access granularity in apic_page (in addition to 32-bit and 64-bit accesses). One caveat of this change is that the generated code is slighly larger. Below is the code generation for apic_get_reg() using gcc-14.2: - Without change: apic_get_reg: 89 f6 mov %esi,%esi 8b 04 37 mov (%rdi,%rsi,1),%eax c3 ret - With change: apic_get_reg: c1 ee 02 shr $0x2,%esi 8b 04 b7 mov (%rdi,%rsi,4),%eax c3 ret lapic.o text size change is shown below: Obj Old-size New-size lapic.o 28800 28832 Signed-off-by: Neeraj Upadhyay --- Changes since v7: - Commit log update. arch/x86/include/asm/apic.h | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 07ba4935e873..b7cbe9ba363e 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -525,26 +525,43 @@ static inline int apic_find_highest_vector(void *bitmap) return -1; } +struct apic_page { + union { + u64 regs64[PAGE_SIZE / 8]; + u32 regs[PAGE_SIZE / 4]; + u8 bytes[PAGE_SIZE]; + }; +} __aligned(PAGE_SIZE); + static inline u32 apic_get_reg(void *regs, int reg) { - return *((u32 *) (regs + reg)); + struct apic_page *ap = regs; + + return ap->regs[reg / 4]; } static inline void apic_set_reg(void *regs, int reg, u32 val) { - *((u32 *) (regs + reg)) = val; + struct apic_page *ap = regs; + + ap->regs[reg / 4] = val; } static __always_inline u64 apic_get_reg64(void *regs, int reg) { + struct apic_page *ap = regs; + BUILD_BUG_ON(reg != APIC_ICR); - return *((u64 *) (regs + reg)); + + return ap->regs64[reg / 8]; } static __always_inline void apic_set_reg64(void *regs, int reg, u64 val) { + struct apic_page *ap = regs; + BUILD_BUG_ON(reg != APIC_ICR); - *((u64 *) (regs + reg)) = val; + ap->regs64[reg / 8] = val; } static inline void apic_clear_vector(int vec, void *bitmap) -- 2.34.1