From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D3E6299AA4 for ; Fri, 11 Jul 2025 13:31:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240679; cv=none; b=iKCkLaZL5Bf8r6vvsOmsQ4e6eutULXzQ9OlzcCGmkivjYfynQvqMZgaYr1sjB6DvREBGh3y/Ad//fMlBbjR1a3CPCRXZ/Q1nfsS8Btolae4x5m0DUTWdE7zBYz9v9CcrX3d33wxzBzu+LyqcLlvReL0BQh2iwuF2jEnVVKnlc4M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240679; c=relaxed/simple; bh=se8LretignPMdLf6tpInpwOsRh7yl2cxJIw/Maxoxs4=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Lw8gT/QvG4ahS4onYwkaldr9+7E809Za78iceDXRD7h9LExfoOLx0NU8ZHELgrwyjRXA0KDynn/UUqqxlli36qG22QwFWw//nf/KFGsEmU3CTPGd8R0CcFQAcUWdthZTkCs6fdI8tIPhPO0dciesKq0AhZkyRVMJN0gZEjRRkAo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDURRR013775 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:27 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:27 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 0/9] add Voyager board support Date: Fri, 11 Jul 2025 21:30:16 +0800 Message-ID: <20250711133025.2192404-1-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 56BDURRR013775 The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including Andes QiLai SoC. This patch series adds minimal device tree files for the QiLai SoC and the Voyager board [1]. Now only support basic uart drivers to boot up into a basic console. Other features will be added later. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ [2] https://lore.kernel.org/all/20250602060747.689824-1-ben717@andestech.com/ --- Changes since v1: * Patch 1 - Deselect two configs for ARCH_ANDES since QiLai SoC does not need them (Prabhakar) - Revert the changes for config ERRATA_ANDES_CMO * Patch 3 - Add reviewed-by Prabhakar * Patch 9 (new) - Gather all the changes for MAINTAINERS in a single patch (Arnd) Link to v1: https://lore.kernel.org/all/20250704081451.2011407-1-ben717@andestech.com/ --- Ben Zong-You Xie (9): riscv: add Andes SoC family Kconfig support dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings dt-bindings: interrupt-controller: add Andes QiLai PLIC dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller dt-bindings: timer: add Andes machine timer riscv: dts: andes: add QiLai SoC device tree riscv: dts: andes: add Voyager board device tree riscv: defconfig: enable Andes SoC MAINTAINERS: Add entry for Andes SoC .../andestech,plicsw.yaml | 54 +++++ .../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/andes.yaml | 25 +++ .../bindings/timer/andestech,plmt0.yaml | 53 +++++ MAINTAINERS | 9 + arch/riscv/Kconfig.socs | 7 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/andes/Makefile | 2 + arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++ arch/riscv/boot/dts/andes/qilai.dtsi | 186 ++++++++++++++++++ arch/riscv/configs/defconfig | 1 + 11 files changed, 367 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml create mode 100644 arch/riscv/boot/dts/andes/Makefile create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi -- 2.34.1