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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e949f2sm787867166b.34.2025.07.14.01.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 01:17:43 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 0/3] clk: tegra: add DFLL support for Tegra 4 Date: Mon, 14 Jul 2025 11:17:10 +0300 Message-ID: <20250714081713.8409-1-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on a ring oscillator and translates voltage changes into frequency compensation changes needed to prevent the CPU from failing and is essential for correct CPU frequency scaling. --- Changes in v2: - dropped 'drivers:' from commit title - aligned naming to Tegra114 --- Svyatoslav Ryhel (3): drivers: cpufreq: add Tegra114 support clk: tegra: add DFLL support for Tegra114 ARM: tegra: Add DFLL clock support on Tegra114 arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 +++++++ drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra124-cpufreq.c | 5 +- include/dt-bindings/reset/tegra114-car.h | 13 +++ 8 files changed, 182 insertions(+), 9 deletions(-) create mode 100644 include/dt-bindings/reset/tegra114-car.h -- 2.48.1