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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3bbe6bd8f8sm13912054a12.38.2025.07.16.08.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:20:28 -0700 (PDT) From: Pankaj Patil To: sboyd@kernel.org, mturquette@baylibre.com, andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, taniya.das@oss.qualcomm.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/7] Add support for Clock controllers for Glymur Date: Wed, 16 Jul 2025 20:50:10 +0530 Message-Id: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDEzOCBTYWx0ZWRfX+kMHnUW0zOHd R+ubAyj+RGgx5rTBjy4mfCMTCqdz4MTh67ORGim4H1ZFvEn4PLZgMhkt/qbCh/54IW3NN7MQRwP GY6+YmnW9woHjUjoSrgJ2Ri7fcjz9hjrRA5RP/koW2JBOEYbwE4aATg37yeAwyoY2aaD5Q3DPPf f+i/LzCzqZO3ryQVzzuascwW5+xQ98/qo6uwRVOIQX2eyETnGqtJwy4AToD9r9ZaYxxmjguw+n3 TAT1IBNkoB+Mukbpk2uAF2t3qqfTHSjEWZxwoH7xPeD5k8omjCNNIvl+HyyOxn7EK6A6oDs1dxV i/zdAu0mrEs9tcFxOFZgt9g/hMUV38RhF4ipkl4CGzZEiFelf7yHc/Vq9H04xln5R22GfrnfiQP Mih5AGaeNlUiMw/sZr3fM2nQS6XGu7/AaUEqL1jP+6VguyjXiRxk0oYZ279zxW134dDzc7t4 X-Proofpoint-GUID: RpDHhhKYo05N3aGKS679q9x3QTN-KAQO X-Authority-Analysis: v=2.4 cv=SZT3duRu c=1 sm=1 tr=0 ts=6877c33e cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ur2kyboyjIJ0vDSx390A:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: RpDHhhKYo05N3aGKS679q9x3QTN-KAQO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_02,2025-07-16_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=969 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160138 Add support for Global clock controller(GCC), TCSR and the RPMH clock controller for the Qualcomm Glymur SoC. Signed-off-by: Taniya Das --- Taniya Das (7): dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs dt-bindings: clock: qcom: Add bindings documentation for the Glymur TCSR clk: qcom: Add TCSR clock driver for Glymur clk: qcom: rpmh: Add support for Glymur rpmh clocks clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL dt-bindings: clock: qcom: document the Glymur Global Clock Controller clk: qcom: gcc: Add support for Global Clock Controller .../bindings/clock/qcom,glymur-gcc.yaml | 122 + .../bindings/clock/qcom,rpmhcc.yaml | 1 + .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 + drivers/clk/qcom/Kconfig | 18 + drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/clk-alpha-pll.h | 6 + drivers/clk/qcom/clk-rpmh.c | 22 + drivers/clk/qcom/gcc-glymur.c | 8623 +++++++++++++++++ drivers/clk/qcom/tcsrcc-glymur.c | 263 + include/dt-bindings/clock/qcom,glymur-gcc.h | 578 ++ .../dt-bindings/clock/qcom,glymur-tcsrcc.h | 24 + 11 files changed, 9662 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml create mode 100644 drivers/clk/qcom/gcc-glymur.c create mode 100644 drivers/clk/qcom/tcsrcc-glymur.c create mode 100644 include/dt-bindings/clock/qcom,glymur-gcc.h create mode 100644 include/dt-bindings/clock/qcom,glymur-tcsrcc.h -- 2.34.1