From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BE73289815; Mon, 21 Jul 2025 08:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753085789; cv=none; b=RQGgLhEtigYzbipyxnpcBz1OFsqJS/oERycQEniHpfSszR8v5NOMtGC+00prn8sw//gorPaCwSngrfa7sZKV4o4MESx3pxKr7MYrZjaGIcEGpy0orERh7P55lb5G5J8xyIjqeJNsD7pJH5xJwCK/JQGbg8our70bC3GkvsvKd4E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753085789; c=relaxed/simple; bh=yeL7Qs9geqC8gCqdN9A4Y2ulSlVIdk/rrZad9e/fGZk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HU5HPeWA0aKMjYmiqc49Zy2t9bsR7UL++bgdG9bQIcEvbDqwWl5spYiXjT2ySjbG52AzfYvCP7XCo8PYspU7tmfFGlXa6Qf7znF5iGf6c0WHR81oX03CVKioa0qw5JamY7mvji7cOODdQEP1EFAXY/0S2lx1ClybyuXWJ6Ee+qw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=bN4B95Kq; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="bN4B95Kq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753085785; bh=yeL7Qs9geqC8gCqdN9A4Y2ulSlVIdk/rrZad9e/fGZk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bN4B95KqC2CPPWDuf5MBrZ1fLMAVgpV/e1zCBK7CK4iBD0dSD1ZyedwlttGGaPy0f Kh+G9gRPMJW/ePOBFFJe+71zpuSrkWoyi2x7Uje9nq/0lPvTMYI/hx/2hm9VieQiqa MZyzuYv3h8JeVrI6wkHrosZIGkVzt4LSMq/vu2Y36B1bn5uN5JbEByfM9BI4Vz1PSJ 6urM4VOi1CPRy/PXQn1WE2KoGWuwQ1ujbUQ9AkWQ0XF5pfNN8RCmz6CWazO+CCyWaE oW6EsQGU+12NwUTHcC2MqwUD/eHMptK3zWLUUV6pycXkEi0mpDO8P38X46OqFB8o4N NUmmnWRl29L3w== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:4487:69c6:40a:81be]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9648817E154C; Mon, 21 Jul 2025 10:16:24 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao Subject: [PATCH 7/9] thermal/drivers/mediatek/lvts: Support MSR offset for 16-bit calibration data Date: Mon, 21 Jul 2025 10:14:57 +0200 Message-Id: <20250721081459.16278-8-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250721081459.16278-1-laura.nao@collabora.com> References: <20250721081459.16278-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On MT8196/MT6991, per-sensor calibration data read from eFuses is 16-bit. When the LVTS controller operates in 16-bit mode, a fixed offset must be added to MSR values during post-processing to obtain correct temperature readings. Introduce a new msr_offset field in lvts_data, program the respective register and apply the offset to the calibration data read from eFuses. Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 8f9da0d5b886..81c8309ff9df 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,7 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_MSROFT(__base) (__base + 0x006C) #define LVTS_ATP0(__base) (__base + 0x0070) #define LVTS_ATP1(__base) (__base + 0x0074) #define LVTS_ATP2(__base) (__base + 0x0078) @@ -144,6 +145,7 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + u16 msr_offset; }; struct lvts_sensor { @@ -212,6 +214,7 @@ static const struct debugfs_reg32 lvts_regs[] = { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_MSROFT), LVTS_DEBUG_FS_REGS(LVTS_ATP0), LVTS_DEBUG_FS_REGS(LVTS_ATP1), LVTS_DEBUG_FS_REGS(LVTS_ATP2), @@ -782,6 +785,8 @@ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl if (gt) { lvts_ctrl->calibration[i] = calib; + if (lvts_ctrl->lvts_data->msr_offset) + lvts_ctrl->calibration[i] += lvts_ctrl->lvts_data->msr_offset; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration; } else { @@ -1096,6 +1101,17 @@ static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) for (i = 0; i < LVTS_SENSOR_MAX; i++) writel(lvts_ctrl->calibration[i], lvts_edata[i]); + /* LVTS_MSROFT : Constant offset applied to MSR values + * for post-processing + * + * Bits: + * + * 20-0 : Constant data added to MSR values + */ + if (lvts_ctrl->lvts_data->msr_offset) + writel(lvts_ctrl->lvts_data->msr_offset, + LVTS_MSROFT(lvts_ctrl->base)); + return 0; } -- 2.39.5